Gerald Mcclain

Array ( [id] => 105313 [patent_doc_number] => 07724600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Electronic fuse programming current generator with on-chip reference' [patent_app_type] => utility [patent_app_number] => 12/043091 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724600.pdf [firstpage_image] =>[orig_patent_app_number] => 12043091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4806848 [patent_doc_number] => 20080170426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Novel ROM Cell Array Structure' [patent_app_type] => utility [patent_app_number] => 12/039711 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2815 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170426.pdf [firstpage_image] =>[orig_patent_app_number] => 12039711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6310023 [patent_doc_number] => 20100110766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'NONVOLATILE MEMORY APPARATUS AND METHOD FOR WRITING DATA IN NONVOLATILE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/524313 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8225 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110766.pdf [firstpage_image] =>[orig_patent_app_number] => 12524313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 312093 [patent_doc_number] => 07529129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Single level cell programming in a multiple level cell non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 12/035552 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529129.pdf [firstpage_image] =>[orig_patent_app_number] => 12035552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4611854 [patent_doc_number] => 07995368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Memory cell architecture' [patent_app_type] => utility [patent_app_number] => 12/034321 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3577 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/995/07995368.pdf [firstpage_image] =>[orig_patent_app_number] => 12034321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 153820 [patent_doc_number] => 07684239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Flash memory device for over-sampling read and interfacing method thereof' [patent_app_type] => utility [patent_app_number] => 12/034055 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/684/07684239.pdf [firstpage_image] =>[orig_patent_app_number] => 12034055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4587738 [patent_doc_number] => 07835220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'PLL circuit for increasing potential difference between ground voltage and reference voltage or power source voltage of oscillation circuit' [patent_app_type] => utility [patent_app_number] => 12/033657 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8677 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/835/07835220.pdf [firstpage_image] =>[orig_patent_app_number] => 12033657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4492484 [patent_doc_number] => 07885140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Clock mode determination in a memory system' [patent_app_type] => utility [patent_app_number] => 12/032249 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13931 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/885/07885140.pdf [firstpage_image] =>[orig_patent_app_number] => 12032249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 36093 [patent_doc_number] => 07787294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Operating method of memory' [patent_app_type] => utility [patent_app_number] => 12/031189 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5250 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787294.pdf [firstpage_image] =>[orig_patent_app_number] => 12031189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4581728 [patent_doc_number] => 07859903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Methods and structures for reading out non-volatile memory using NVM cells as a load element' [patent_app_type] => utility [patent_app_number] => 12/031691 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 6240 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859903.pdf [firstpage_image] =>[orig_patent_app_number] => 12031691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 55610 [patent_doc_number] => 07773445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Reading method and circuit for a non-volatile memory device based on the adaptive generation of a reference electrical quantity' [patent_app_type] => utility [patent_app_number] => 12/031645 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4917 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773445.pdf [firstpage_image] =>[orig_patent_app_number] => 12031645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 212457 [patent_doc_number] => 07623369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Method and system for providing a magnetic memory structure utilizing spin transfer' [patent_app_type] => utility [patent_app_number] => 12/030541 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/623/07623369.pdf [firstpage_image] =>[orig_patent_app_number] => 12030541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6589111 [patent_doc_number] => 20100097845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/527993 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14943 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097845.pdf [firstpage_image] =>[orig_patent_app_number] => 12527993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4696896 [patent_doc_number] => 20080219080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Memory Device with Reduced Standby Power Consumption and Method for Operating Same' [patent_app_type] => utility [patent_app_number] => 12/019669 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4447 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20080219080.pdf [firstpage_image] =>[orig_patent_app_number] => 12019669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 134070 [patent_doc_number] => 07701781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 12/019245 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8125 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701781.pdf [firstpage_image] =>[orig_patent_app_number] => 12019245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4763834 [patent_doc_number] => 20080175045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'DEPLETION-MODE MOSFET CIRCUIT AND APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/019391 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175045.pdf [firstpage_image] =>[orig_patent_app_number] => 12019391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 76580 [patent_doc_number] => 07751240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Memory device with negative thresholds' [patent_app_type] => utility [patent_app_number] => 12/019011 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7145 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751240.pdf [firstpage_image] =>[orig_patent_app_number] => 12019011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 198909 [patent_doc_number] => 07639554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor device and method of testing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/018993 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 18073 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639554.pdf [firstpage_image] =>[orig_patent_app_number] => 12018993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 46527 [patent_doc_number] => 07778078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Memory system and control method thereof' [patent_app_type] => utility [patent_app_number] => 12/019227 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778078.pdf [firstpage_image] =>[orig_patent_app_number] => 12019227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5444623 [patent_doc_number] => 20090045849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'DATA BUS SENSE AMPLIFIER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/018775 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4339 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045849.pdf [firstpage_image] =>[orig_patent_app_number] => 12018775 [rel_patent_id] =>[rel_patent_doc_number] =>)