Gerald Mcclain

Array ( [id] => 405514 [patent_doc_number] => 07289349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Resistance variable memory element with threshold device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/601747 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4291 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/289/07289349.pdf [firstpage_image] =>[orig_patent_app_number] => 11601747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4987240 [patent_doc_number] => 20070153578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'METHOD FOR ACCESSING IN READING, WRITING AND PROGRAMMING TO A NAND NON-VOLATILE MEMORY ELECTRONIC DEVICE MONOLITHICALLY INTEGRATED ON SEMICONCTOR' [patent_app_type] => utility [patent_app_number] => 11/561799 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6874 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153578.pdf [firstpage_image] =>[orig_patent_app_number] => 11561799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5094136 [patent_doc_number] => 20070115745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'FUSE BOX, METHOD OF FORMING A FUSE BOX, AND FUSE CUTTING METHOD' [patent_app_type] => utility [patent_app_number] => 11/559759 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4523 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115745.pdf [firstpage_image] =>[orig_patent_app_number] => 11559759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 360660 [patent_doc_number] => 07486539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Memory array using mechanical switch, method for controlling the same, display apparatus using mechanical switch, and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 11/556451 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/486/07486539.pdf [firstpage_image] =>[orig_patent_app_number] => 11556451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4823145 [patent_doc_number] => 20080123406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Dynamic Program and Read Adjustment for Multi-Level Cell Memory Array' [patent_app_type] => utility [patent_app_number] => 11/555849 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7512 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20080123406.pdf [firstpage_image] =>[orig_patent_app_number] => 11555849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 206384 [patent_doc_number] => 07630243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/094379 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7876 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/630/07630243.pdf [firstpage_image] =>[orig_patent_app_number] => 12094379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4976031 [patent_doc_number] => 20070217262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Segmented Column Virtual Ground Scheme In A Static Random Access Memory (SRAM) Circuit' [patent_app_type] => utility [patent_app_number] => 11/552655 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4732 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217262.pdf [firstpage_image] =>[orig_patent_app_number] => 11552655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 254484 [patent_doc_number] => 07581127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Interface circuit system and method for performing power saving operations during a command-related latency' [patent_app_type] => utility [patent_app_number] => 11/584179 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17679 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/581/07581127.pdf [firstpage_image] =>[orig_patent_app_number] => 11584179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5090612 [patent_doc_number] => 20070230251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Nonvolatile Semiconductor Memory' [patent_app_type] => utility [patent_app_number] => 11/550335 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13453 [patent_no_of_claims] => 122 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230251.pdf [firstpage_image] =>[orig_patent_app_number] => 11550335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5251820 [patent_doc_number] => 20070133276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Operating array cells with matched reference cells' [patent_app_type] => utility [patent_app_number] => 11/580995 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3502 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133276.pdf [firstpage_image] =>[orig_patent_app_number] => 11580995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5033217 [patent_doc_number] => 20070097756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor integrated circuit and leak current reducing method' [patent_app_type] => utility [patent_app_number] => 11/546955 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20398 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097756.pdf [firstpage_image] =>[orig_patent_app_number] => 11546955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5218592 [patent_doc_number] => 20070159903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Memory devices including floating body transistor capacitorless memory cells and related methods' [patent_app_type] => utility [patent_app_number] => 11/546421 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5351 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159903.pdf [firstpage_image] =>[orig_patent_app_number] => 11546421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4984362 [patent_doc_number] => 20070088921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Semiconductor memory devices including mode registers and systems including the same' [patent_app_type] => utility [patent_app_number] => 11/546625 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5369 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088921.pdf [firstpage_image] =>[orig_patent_app_number] => 11546625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5158696 [patent_doc_number] => 20070171740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Semiconductor memory module and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/540607 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8885 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171740.pdf [firstpage_image] =>[orig_patent_app_number] => 11540607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4969863 [patent_doc_number] => 20070109865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Radiation tolerant combinational logic cell' [patent_app_type] => utility [patent_app_number] => 11/527375 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10102 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109865.pdf [firstpage_image] =>[orig_patent_app_number] => 11527375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 588616 [patent_doc_number] => 07457185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Semiconductor memory device with advanced refresh control' [patent_app_type] => utility [patent_app_number] => 11/525013 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4339 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457185.pdf [firstpage_image] =>[orig_patent_app_number] => 11525013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 342045 [patent_doc_number] => 07501803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Synchronized boost signal apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/524615 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4249 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501803.pdf [firstpage_image] =>[orig_patent_app_number] => 11524615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4656264 [patent_doc_number] => 20080025125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit' [patent_app_type] => utility [patent_app_number] => 11/524812 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025125.pdf [firstpage_image] =>[orig_patent_app_number] => 11524812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 245052 [patent_doc_number] => 07590796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'System and method for power management in memory systems' [patent_app_type] => utility [patent_app_number] => 11/524811 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590796.pdf [firstpage_image] =>[orig_patent_app_number] => 11524811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4656262 [patent_doc_number] => 20080025123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits' [patent_app_type] => utility [patent_app_number] => 11/524716 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025123.pdf [firstpage_image] =>[orig_patent_app_number] => 11524716 [rel_patent_id] =>[rel_patent_doc_number] =>)