Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5181892 [patent_doc_number] => 20070053235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/460299 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5625 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20070053235.pdf [firstpage_image] =>[orig_patent_app_number] => 11460299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460299
Semiconductor memory device Jul 26, 2006 Issued
Array ( [id] => 5153129 [patent_doc_number] => 20070036011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'SHARED REDUNDANT MEMORY ARCHITECTURE AND MEMORY SYSTEM INCORPORATING SAME' [patent_app_type] => utility [patent_app_number] => 11/460071 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3669 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20070036011.pdf [firstpage_image] =>[orig_patent_app_number] => 11460071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460071
Shared redundant memory architecture and memory system incorporating same Jul 25, 2006 Issued
Array ( [id] => 357103 [patent_doc_number] => 07489545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Memory utilizing oxide-nitride nanolaminates' [patent_app_type] => utility [patent_app_number] => 11/492749 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 13740 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489545.pdf [firstpage_image] =>[orig_patent_app_number] => 11492749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492749
Memory utilizing oxide-nitride nanolaminates Jul 24, 2006 Issued
Array ( [id] => 5240973 [patent_doc_number] => 20070019464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'MAGNETIC MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/459479 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10317 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019464.pdf [firstpage_image] =>[orig_patent_app_number] => 11459479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459479
Magnetic memory device Jul 23, 2006 Issued
Array ( [id] => 4908423 [patent_doc_number] => 20080019189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Method of High-Performance Flash Memory Data Transfer' [patent_app_type] => utility [patent_app_number] => 11/458422 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12211 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019189.pdf [firstpage_image] =>[orig_patent_app_number] => 11458422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458422
Method of high-performance flash memory data transfer Jul 18, 2006 Issued
Array ( [id] => 4908404 [patent_doc_number] => 20080019170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'INTEGRATED CIRCUIT HAVING MEMORY HAVING A STEP-LIKE PROGRAMMING CHARACTERISTIC' [patent_app_type] => utility [patent_app_number] => 11/488869 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15058 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019170.pdf [firstpage_image] =>[orig_patent_app_number] => 11488869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/488869
Integrated circuit having memory having a step-like programming characteristic Jul 17, 2006 Issued
Array ( [id] => 409951 [patent_doc_number] => 07286434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor memory device with shift register-based refresh address generation circuit' [patent_app_type] => utility [patent_app_number] => 11/486002 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14856 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286434.pdf [firstpage_image] =>[orig_patent_app_number] => 11486002 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486002
Semiconductor memory device with shift register-based refresh address generation circuit Jul 13, 2006 Issued
Array ( [id] => 5251831 [patent_doc_number] => 20070133287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Threshold value read method of nonvolatile semiconductor memory device and nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/485483 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133287.pdf [firstpage_image] =>[orig_patent_app_number] => 11485483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485483
Threshold value read method of nonvolatile semiconductor memory device and nonvolatile semiconductor memory device Jul 12, 2006 Issued
Array ( [id] => 5074200 [patent_doc_number] => 20070014175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'DRAM and method for partially refreshing memory cell array' [patent_app_type] => utility [patent_app_number] => 11/485565 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4273 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20070014175.pdf [firstpage_image] =>[orig_patent_app_number] => 11485565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485565
DRAM and method for partially refreshing memory cell array Jul 11, 2006 Issued
Array ( [id] => 5181885 [patent_doc_number] => 20070053228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Flash memory device and voltage generating circuit for the same' [patent_app_type] => utility [patent_app_number] => 11/482447 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5191 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20070053228.pdf [firstpage_image] =>[orig_patent_app_number] => 11482447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482447
Flash memory device and voltage generating circuit for the same Jul 6, 2006 Issued
Array ( [id] => 4993457 [patent_doc_number] => 20070008802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Dynamic random access memory and communications terminal including the same' [patent_app_type] => utility [patent_app_number] => 11/482141 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008802.pdf [firstpage_image] =>[orig_patent_app_number] => 11482141 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482141
Dynamic random access memory and communications terminal including the same Jul 6, 2006 Issued
Array ( [id] => 271496 [patent_doc_number] => 07564735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Memory device, and method for operating a memory device' [patent_app_type] => utility [patent_app_number] => 11/481157 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3944 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564735.pdf [firstpage_image] =>[orig_patent_app_number] => 11481157 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/481157
Memory device, and method for operating a memory device Jul 4, 2006 Issued
Array ( [id] => 5074205 [patent_doc_number] => 20070014180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'DEVICE AND METHOD FOR SELECTING 1-ROW AND 2-ROW ACTIVATION' [patent_app_type] => utility [patent_app_number] => 11/428497 [patent_app_country] => US [patent_app_date] => 2006-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20070014180.pdf [firstpage_image] =>[orig_patent_app_number] => 11428497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428497
Device and method for selecting 1-row and 2-row activation Jul 2, 2006 Issued
Array ( [id] => 5054779 [patent_doc_number] => 20070057700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'CAM CELLS AND CAM MATRIX MADE UP OF A NETWORK OF SUCH MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/428471 [patent_app_country] => US [patent_app_date] => 2006-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2997 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057700.pdf [firstpage_image] =>[orig_patent_app_number] => 11428471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428471
CAM cells and CAM matrix made up of a network of such memory cells Jul 2, 2006 Issued
Array ( [id] => 309419 [patent_doc_number] => 07533222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Dual-port SRAM memory using single-port memory cell' [patent_app_type] => utility [patent_app_number] => 11/427785 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8259 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533222.pdf [firstpage_image] =>[orig_patent_app_number] => 11427785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/427785
Dual-port SRAM memory using single-port memory cell Jun 28, 2006 Issued
Array ( [id] => 5240976 [patent_doc_number] => 20070019467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/476023 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 20161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019467.pdf [firstpage_image] =>[orig_patent_app_number] => 11476023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/476023
Semiconductor memory device Jun 27, 2006 Issued
Array ( [id] => 850462 [patent_doc_number] => 07382676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Method of forming a programmable voltage regulator and structure therefor' [patent_app_type] => utility [patent_app_number] => 11/474473 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/382/07382676.pdf [firstpage_image] =>[orig_patent_app_number] => 11474473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474473
Method of forming a programmable voltage regulator and structure therefor Jun 25, 2006 Issued
Array ( [id] => 527952 [patent_doc_number] => 07190608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Sensing of resistance variable memory devices' [patent_app_type] => utility [patent_app_number] => 11/473308 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9410 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190608.pdf [firstpage_image] =>[orig_patent_app_number] => 11473308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/473308
Sensing of resistance variable memory devices Jun 22, 2006 Issued
Array ( [id] => 5197889 [patent_doc_number] => 20070297207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Methods and apparatus for content addressable memory arrays including shared match lines' [patent_app_type] => utility [patent_app_number] => 11/473417 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2577 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297207.pdf [firstpage_image] =>[orig_patent_app_number] => 11473417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/473417
Methods and apparatus for content addressable memory arrays including shared match lines Jun 21, 2006 Issued
Array ( [id] => 4969874 [patent_doc_number] => 20070109876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 11/471681 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17320 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109876.pdf [firstpage_image] =>[orig_patent_app_number] => 11471681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471681
Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same Jun 20, 2006 Issued
Menu