Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5893663 [patent_doc_number] => 20060002201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Active termination control' [patent_app_type] => utility [patent_app_number] => 11/216369 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9019 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002201.pdf [firstpage_image] =>[orig_patent_app_number] => 11216369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216369
Active termination control Aug 30, 2005 Issued
Array ( [id] => 5900588 [patent_doc_number] => 20060044900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method for testing an integrated semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/212919 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6172 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044900.pdf [firstpage_image] =>[orig_patent_app_number] => 11212919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212919
Method for testing an integrated semiconductor memory Aug 28, 2005 Issued
Array ( [id] => 526359 [patent_doc_number] => 07193923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Semiconductor memory device and access method and memory control system for same' [patent_app_type] => utility [patent_app_number] => 11/201309 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7586 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193923.pdf [firstpage_image] =>[orig_patent_app_number] => 11201309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201309
Semiconductor memory device and access method and memory control system for same Aug 10, 2005 Issued
Array ( [id] => 5879818 [patent_doc_number] => 20060028900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/197227 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3867 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028900.pdf [firstpage_image] =>[orig_patent_app_number] => 11197227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197227
Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof Aug 3, 2005 Issued
Array ( [id] => 482310 [patent_doc_number] => 07224612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/194799 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 68 [patent_no_of_words] => 45189 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224612.pdf [firstpage_image] =>[orig_patent_app_number] => 11194799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194799
Nonvolatile semiconductor memory device Aug 1, 2005 Issued
Array ( [id] => 5053036 [patent_doc_number] => 20070033581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Situation sensitive memory performance' [patent_app_type] => utility [patent_app_number] => 11/196161 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6612 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033581.pdf [firstpage_image] =>[orig_patent_app_number] => 11196161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196161
Situation sensitive memory performance Aug 1, 2005 Issued
Array ( [id] => 5767895 [patent_doc_number] => 20050265060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Adjustable timing circuit of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/195308 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4057 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20050265060.pdf [firstpage_image] =>[orig_patent_app_number] => 11195308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195308
Adjustable timing circuit of an integrated circuit Aug 1, 2005 Abandoned
Array ( [id] => 5765069 [patent_doc_number] => 20060018153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Operating array cells with matched reference cells' [patent_app_type] => utility [patent_app_number] => 11/194394 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20060018153.pdf [firstpage_image] =>[orig_patent_app_number] => 11194394 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194394
Operating array cells with matched reference cells Jul 31, 2005 Issued
Array ( [id] => 754306 [patent_doc_number] => 07023737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'System for programming non-volatile memory with self-adjusting maximum program loop' [patent_app_type] => utility [patent_app_number] => 11/194827 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 10365 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023737.pdf [firstpage_image] =>[orig_patent_app_number] => 11194827 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194827
System for programming non-volatile memory with self-adjusting maximum program loop Jul 31, 2005 Issued
Array ( [id] => 537632 [patent_doc_number] => 07184304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Nonvolatile semiconductor memory device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/191963 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/184/07184304.pdf [firstpage_image] =>[orig_patent_app_number] => 11191963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191963
Nonvolatile semiconductor memory device and method for fabricating the same Jul 28, 2005 Issued
Array ( [id] => 5445307 [patent_doc_number] => 20090046533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Multichip system and method of transferring data therein' [patent_app_type] => utility [patent_app_number] => 11/665635 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5606 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046533.pdf [firstpage_image] =>[orig_patent_app_number] => 11665635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/665635
Multichip system and method of transferring data therein Jul 25, 2005 Issued
Array ( [id] => 784510 [patent_doc_number] => 06992910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-31 [patent_title] => 'Magnetic random access memory with three or more stacked toggle memory cells and method for writing a selected cell' [patent_app_type] => utility [patent_app_number] => 11/185331 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 14 [patent_no_of_words] => 6470 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992910.pdf [firstpage_image] =>[orig_patent_app_number] => 11185331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185331
Magnetic random access memory with three or more stacked toggle memory cells and method for writing a selected cell Jul 19, 2005 Issued
Array ( [id] => 758790 [patent_doc_number] => 07020043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/180933 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2873 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020043.pdf [firstpage_image] =>[orig_patent_app_number] => 11180933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180933
Semiconductor memory device Jul 11, 2005 Issued
Array ( [id] => 7068260 [patent_doc_number] => 20050243643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Semiconductor memory device invalidating improper control command' [patent_app_type] => utility [patent_app_number] => 11/174472 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 16495 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20050243643.pdf [firstpage_image] =>[orig_patent_app_number] => 11174472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174472
Semiconductor memory device invalidating improper control command Jul 5, 2005 Issued
Array ( [id] => 5078156 [patent_doc_number] => 20070121380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'LOCATION-SPECIFIC NAND (LS NAND) MEMORY TECHNOLOGY AND CELLS' [patent_app_type] => utility [patent_app_number] => 11/174333 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9963 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121380.pdf [firstpage_image] =>[orig_patent_app_number] => 11174333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174333
Location-specific NAND (LS NAND) memory technology and cells Jul 4, 2005 Issued
Array ( [id] => 503250 [patent_doc_number] => 07209383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Magnetic random access memory array having bit/word lines for shared write select and read operations' [patent_app_type] => utility [patent_app_number] => 11/159858 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4317 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209383.pdf [firstpage_image] =>[orig_patent_app_number] => 11159858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159858
Magnetic random access memory array having bit/word lines for shared write select and read operations Jun 22, 2005 Issued
Array ( [id] => 5687108 [patent_doc_number] => 20060285423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Volatile memory cell two-pass writing method' [patent_app_type] => utility [patent_app_number] => 11/157317 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8774 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20060285423.pdf [firstpage_image] =>[orig_patent_app_number] => 11157317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157317
Volatile memory cell two-pass writing method Jun 19, 2005 Issued
Array ( [id] => 5812171 [patent_doc_number] => 20060083045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Semiconductor memory device with MOS transistors each having floating gate and control gate' [patent_app_type] => utility [patent_app_number] => 11/153531 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 28647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083045.pdf [firstpage_image] =>[orig_patent_app_number] => 11153531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153531
Semiconductor memory device with MOS transistors each having floating gate and control gate Jun 15, 2005 Issued
Array ( [id] => 487006 [patent_doc_number] => 07221616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Word line driver circuits for use in semiconductor memory and driving method thereof' [patent_app_type] => utility [patent_app_number] => 11/154621 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4206 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221616.pdf [firstpage_image] =>[orig_patent_app_number] => 11154621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/154621
Word line driver circuits for use in semiconductor memory and driving method thereof Jun 15, 2005 Issued
Array ( [id] => 5687109 [patent_doc_number] => 20060285424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips' [patent_app_type] => utility [patent_app_number] => 11/152769 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8936 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20060285424.pdf [firstpage_image] =>[orig_patent_app_number] => 11152769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152769
High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips Jun 14, 2005 Issued
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