
Gerald Mcclain
Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )
| Most Active Art Unit | 3652 |
| Art Unit(s) | 3653, 3652 |
| Total Applications | 1263 |
| Issued Applications | 964 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 665600
[patent_doc_number] => 07102943
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/152101
[patent_app_country] => US
[patent_app_date] => 2005-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5424
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/102/07102943.pdf
[firstpage_image] =>[orig_patent_app_number] => 11152101
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/152101 | Non-volatile semiconductor memory device | Jun 14, 2005 | Issued |
Array
(
[id] => 6930056
[patent_doc_number] => 20050281090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Memory architecture with segmented writing lines'
[patent_app_type] => utility
[patent_app_number] => 11/152033
[patent_app_country] => US
[patent_app_date] => 2005-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4119
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0281/20050281090.pdf
[firstpage_image] =>[orig_patent_app_number] => 11152033
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/152033 | Memory architecture with segmented writing lines | Jun 13, 2005 | Issued |
Array
(
[id] => 5879796
[patent_doc_number] => 20060028878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Programming and evaluating through PMOS injection'
[patent_app_type] => utility
[patent_app_number] => 11/151568
[patent_app_country] => US
[patent_app_date] => 2005-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2670
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0028/20060028878.pdf
[firstpage_image] =>[orig_patent_app_number] => 11151568
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/151568 | Programming and evaluating through PMOS injection | Jun 12, 2005 | Issued |
Array
(
[id] => 710513
[patent_doc_number] => 07061805
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'P-channel NAND flash memory and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/160035
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5394
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/061/07061805.pdf
[firstpage_image] =>[orig_patent_app_number] => 11160035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/160035 | P-channel NAND flash memory and operating method thereof | Jun 5, 2005 | Issued |
Array
(
[id] => 624936
[patent_doc_number] => 07139204
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-11-21
[patent_title] => 'Method and system for testing a dual-port memory at speed in a stressed environment'
[patent_app_type] => utility
[patent_app_number] => 11/146829
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6134
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/139/07139204.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146829
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146829 | Method and system for testing a dual-port memory at speed in a stressed environment | Jun 5, 2005 | Issued |
Array
(
[id] => 5879802
[patent_doc_number] => 20060028884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/144767
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8724
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0028/20060028884.pdf
[firstpage_image] =>[orig_patent_app_number] => 11144767
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/144767 | Nonvolatile semiconductor memory device | Jun 5, 2005 | Issued |
Array
(
[id] => 6957013
[patent_doc_number] => 20050213383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 11/138290
[patent_app_country] => US
[patent_app_date] => 2005-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14090
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0213/20050213383.pdf
[firstpage_image] =>[orig_patent_app_number] => 11138290
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/138290 | Nonvolatile semiconductor memory | May 26, 2005 | Issued |
Array
(
[id] => 5767946
[patent_doc_number] => 20050265087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Power supply boost control device and method for identifying and judging fault location in power supply boost control device'
[patent_app_type] => utility
[patent_app_number] => 11/134379
[patent_app_country] => US
[patent_app_date] => 2005-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6425
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0265/20050265087.pdf
[firstpage_image] =>[orig_patent_app_number] => 11134379
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/134379 | Power supply boost control device and method for identifying and judging fault location in power supply boost control device | May 22, 2005 | Issued |
Array
(
[id] => 704668
[patent_doc_number] => 07064977
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-06-20
[patent_title] => 'Reference cells for TCCT based memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/134004
[patent_app_country] => US
[patent_app_date] => 2005-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 5636
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/064/07064977.pdf
[firstpage_image] =>[orig_patent_app_number] => 11134004
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/134004 | Reference cells for TCCT based memory cells | May 19, 2005 | Issued |
Array
(
[id] => 5681934
[patent_doc_number] => 20060198204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Fast read port for register file'
[patent_app_type] => utility
[patent_app_number] => 11/130929
[patent_app_country] => US
[patent_app_date] => 2005-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5372
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20060198204.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130929
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130929 | Fast read port for register file | May 16, 2005 | Issued |
Array
(
[id] => 545281
[patent_doc_number] => 07173864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Data latch circuit and semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/131095
[patent_app_country] => US
[patent_app_date] => 2005-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4654
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173864.pdf
[firstpage_image] =>[orig_patent_app_number] => 11131095
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/131095 | Data latch circuit and semiconductor device using the same | May 16, 2005 | Issued |
Array
(
[id] => 430071
[patent_doc_number] => 07269079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory'
[patent_app_type] => utility
[patent_app_number] => 11/129315
[patent_app_country] => US
[patent_app_date] => 2005-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 3669
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269079.pdf
[firstpage_image] =>[orig_patent_app_number] => 11129315
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/129315 | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory | May 15, 2005 | Issued |
Array
(
[id] => 5731496
[patent_doc_number] => 20060256610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Nonvolatile memory system using magneto-resistive random access memory (MRAM)'
[patent_app_type] => utility
[patent_app_number] => 11/130351
[patent_app_country] => US
[patent_app_date] => 2005-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2785
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20060256610.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130351
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130351 | Nonvolatile memory system using magneto-resistive random access memory (MRAM) | May 15, 2005 | Issued |
Array
(
[id] => 7109760
[patent_doc_number] => 20050207214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/130464
[patent_app_country] => US
[patent_app_date] => 2005-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11614
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20050207214.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130464
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130464 | Semiconductor memory device | May 15, 2005 | Issued |
Array
(
[id] => 179987
[patent_doc_number] => 07657703
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-02-02
[patent_title] => 'Double density content addressable memory (CAM) lookup scheme'
[patent_app_type] => utility
[patent_app_number] => 11/118697
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7348
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/657/07657703.pdf
[firstpage_image] =>[orig_patent_app_number] => 11118697
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/118697 | Double density content addressable memory (CAM) lookup scheme | Apr 27, 2005 | Issued |
Array
(
[id] => 494448
[patent_doc_number] => 07215564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-08
[patent_title] => 'Semiconductor memory component in cross-point architecture'
[patent_app_type] => utility
[patent_app_number] => 11/115953
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2828
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/215/07215564.pdf
[firstpage_image] =>[orig_patent_app_number] => 11115953
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/115953 | Semiconductor memory component in cross-point architecture | Apr 26, 2005 | Issued |
Array
(
[id] => 5652784
[patent_doc_number] => 20060138519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Float gate memory device'
[patent_app_type] => utility
[patent_app_number] => 11/115301
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6097
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20060138519.pdf
[firstpage_image] =>[orig_patent_app_number] => 11115301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/115301 | Float gate memory device | Apr 26, 2005 | Issued |
Array
(
[id] => 569055
[patent_doc_number] => 07161856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-09
[patent_title] => 'Circuit for generating data strobe signal of semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/115351
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2868
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/161/07161856.pdf
[firstpage_image] =>[orig_patent_app_number] => 11115351
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/115351 | Circuit for generating data strobe signal of semiconductor memory device | Apr 26, 2005 | Issued |
Array
(
[id] => 367480
[patent_doc_number] => 07480165
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-20
[patent_title] => 'Microcontroller with programmable logic'
[patent_app_type] => utility
[patent_app_number] => 11/103416
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2114
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/480/07480165.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103416
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103416 | Microcontroller with programmable logic | Apr 10, 2005 | Issued |
Array
(
[id] => 531672
[patent_doc_number] => 07187598
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-06
[patent_title] => 'Device having an interface and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/098873
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3649
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/187/07187598.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098873
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098873 | Device having an interface and method thereof | Apr 4, 2005 | Issued |