
Gerald Mcclain
Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )
| Most Active Art Unit | 3652 |
| Art Unit(s) | 3653, 3652 |
| Total Applications | 1263 |
| Issued Applications | 964 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7245433
[patent_doc_number] => 20050141284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase'
[patent_app_type] => utility
[patent_app_number] => 10/947131
[patent_app_country] => US
[patent_app_date] => 2004-09-23
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[pdf_file] => publications/A1/0141/20050141284.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/947131 | Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase | Sep 22, 2004 | Issued |
Array
(
[id] => 732660
[patent_doc_number] => 07042758
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Magnetic cell and magnetic memory'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10943835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/943835 | Magnetic cell and magnetic memory | Sep 19, 2004 | Issued |
Array
(
[id] => 689030
[patent_doc_number] => 07079425
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[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Data output circuit in a semiconductor memory device and control method of a data output circuit'
[patent_app_type] => utility
[patent_app_number] => 10/942829
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/942829 | Data output circuit in a semiconductor memory device and control method of a data output circuit | Sep 16, 2004 | Issued |
Array
(
[id] => 736765
[patent_doc_number] => 07038969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Semiconductor memory having a spare memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/940635
[patent_app_country] => US
[patent_app_date] => 2004-09-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/940635 | Semiconductor memory having a spare memory cell | Sep 14, 2004 | Issued |
Array
(
[id] => 7606548
[patent_doc_number] => 07099170
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[patent_issue_date] => 2006-08-29
[patent_title] => 'Reduced turn-on current content addressable memory (CAM) device and method'
[patent_app_type] => utility
[patent_app_number] => 10/940129
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/940129 | Reduced turn-on current content addressable memory (CAM) device and method | Sep 13, 2004 | Issued |
Array
(
[id] => 7115531
[patent_doc_number] => 20050068832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Semiconductor storage device'
[patent_app_type] => utility
[patent_app_number] => 10/938635
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[firstpage_image] =>[orig_patent_app_number] => 10938635
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938635 | Semiconductor storage device | Sep 12, 2004 | Abandoned |
Array
(
[id] => 7196194
[patent_doc_number] => 20050041481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Clamping circuit for the Vpop voltage used to program antifuses'
[patent_app_type] => utility
[patent_app_number] => 10/932271
[patent_app_country] => US
[patent_app_date] => 2004-09-02
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[firstpage_image] =>[orig_patent_app_number] => 10932271
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932271 | Method of programming a programmable element in a memory device | Sep 1, 2004 | Issued |
Array
(
[id] => 7196211
[patent_doc_number] => 20050041485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Adjustable timing circuit of an integrated circut'
[patent_app_type] => utility
[patent_app_number] => 10/931427
[patent_app_country] => US
[patent_app_date] => 2004-09-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931427 | Adjustable timing circuit of an integrated circuit | Aug 31, 2004 | Issued |
Array
(
[id] => 5900594
[patent_doc_number] => 20060044906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Sensing of resistance variable memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/931129
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[firstpage_image] =>[orig_patent_app_number] => 10931129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931129 | Sensing of resistance variable memory devices | Aug 31, 2004 | Issued |
Array
(
[id] => 931967
[patent_doc_number] => 06980478
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[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Zero-enabled fuse-set'
[patent_app_type] => utility
[patent_app_number] => 10/931735
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931735 | Zero-enabled fuse-set | Aug 31, 2004 | Issued |
Array
(
[id] => 596559
[patent_doc_number] => 07440317
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[patent_issue_date] => 2008-10-21
[patent_title] => 'One transistor SOI non-volatile random access memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/931367
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[pdf_file] => patents/07/440/07440317.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931367
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931367 | One transistor SOI non-volatile random access memory cell | Aug 30, 2004 | Issued |
Array
(
[id] => 7081847
[patent_doc_number] => 20050047227
[patent_country] => US
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[patent_issue_date] => 2005-03-03
[patent_title] => 'Semiconductor device and ID generator configured as semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/924735 | Semiconductor device and ID generator configured as semiconductor device | Aug 23, 2004 | Abandoned |
Array
(
[id] => 763718
[patent_doc_number] => 07012841
[patent_country] => US
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[patent_title] => 'Circuit and method for current pulse compensation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/924631 | Circuit and method for current pulse compensation | Aug 23, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050047221
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[patent_title] => 'Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation'
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Array
(
[id] => 5589781
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[patent_title] => 'Read command triggered synchronization circuitry'
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Array
(
[id] => 969858
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[patent_title] => 'Nonvolatile semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/920161 | Nonvolatile semiconductor memory device | Aug 17, 2004 | Issued |
Array
(
[id] => 644092
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[patent_title] => 'Reference cells for TCCT based memory cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/919956 | Reference cells for TCCT based memory cells | Aug 16, 2004 | Issued |
Array
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Array
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[patent_title] => 'Systems for programmable memory using silicided poly-silicon fuses'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/915430 | Associative memory apparatus for searching data in which manhattan distance is minimum | Aug 10, 2004 | Issued |