Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7245433 [patent_doc_number] => 20050141284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase' [patent_app_type] => utility [patent_app_number] => 10/947131 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141284.pdf [firstpage_image] =>[orig_patent_app_number] => 10947131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947131
Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase Sep 22, 2004 Issued
Array ( [id] => 732660 [patent_doc_number] => 07042758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Magnetic cell and magnetic memory' [patent_app_type] => utility [patent_app_number] => 10/943835 [patent_app_country] => US [patent_app_date] => 2004-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 9559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042758.pdf [firstpage_image] =>[orig_patent_app_number] => 10943835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/943835
Magnetic cell and magnetic memory Sep 19, 2004 Issued
Array ( [id] => 689030 [patent_doc_number] => 07079425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Data output circuit in a semiconductor memory device and control method of a data output circuit' [patent_app_type] => utility [patent_app_number] => 10/942829 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6446 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/079/07079425.pdf [firstpage_image] =>[orig_patent_app_number] => 10942829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942829
Data output circuit in a semiconductor memory device and control method of a data output circuit Sep 16, 2004 Issued
Array ( [id] => 736765 [patent_doc_number] => 07038969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Semiconductor memory having a spare memory cell' [patent_app_type] => utility [patent_app_number] => 10/940635 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 17368 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038969.pdf [firstpage_image] =>[orig_patent_app_number] => 10940635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940635
Semiconductor memory having a spare memory cell Sep 14, 2004 Issued
Array ( [id] => 7606548 [patent_doc_number] => 07099170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Reduced turn-on current content addressable memory (CAM) device and method' [patent_app_type] => utility [patent_app_number] => 10/940129 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099170.pdf [firstpage_image] =>[orig_patent_app_number] => 10940129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940129
Reduced turn-on current content addressable memory (CAM) device and method Sep 13, 2004 Issued
Array ( [id] => 7115531 [patent_doc_number] => 20050068832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/938635 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6515 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068832.pdf [firstpage_image] =>[orig_patent_app_number] => 10938635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/938635
Semiconductor storage device Sep 12, 2004 Abandoned
Array ( [id] => 7196194 [patent_doc_number] => 20050041481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Clamping circuit for the Vpop voltage used to program antifuses' [patent_app_type] => utility [patent_app_number] => 10/932271 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041481.pdf [firstpage_image] =>[orig_patent_app_number] => 10932271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932271
Method of programming a programmable element in a memory device Sep 1, 2004 Issued
Array ( [id] => 7196211 [patent_doc_number] => 20050041485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Adjustable timing circuit of an integrated circut' [patent_app_type] => utility [patent_app_number] => 10/931427 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4030 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041485.pdf [firstpage_image] =>[orig_patent_app_number] => 10931427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931427
Adjustable timing circuit of an integrated circuit Aug 31, 2004 Issued
Array ( [id] => 5900594 [patent_doc_number] => 20060044906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Sensing of resistance variable memory devices' [patent_app_type] => utility [patent_app_number] => 10/931129 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9503 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044906.pdf [firstpage_image] =>[orig_patent_app_number] => 10931129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931129
Sensing of resistance variable memory devices Aug 31, 2004 Issued
Array ( [id] => 931967 [patent_doc_number] => 06980478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Zero-enabled fuse-set' [patent_app_type] => utility [patent_app_number] => 10/931735 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7979 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/980/06980478.pdf [firstpage_image] =>[orig_patent_app_number] => 10931735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931735
Zero-enabled fuse-set Aug 31, 2004 Issued
Array ( [id] => 596559 [patent_doc_number] => 07440317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'One transistor SOI non-volatile random access memory cell' [patent_app_type] => utility [patent_app_number] => 10/931367 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 9082 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440317.pdf [firstpage_image] =>[orig_patent_app_number] => 10931367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931367
One transistor SOI non-volatile random access memory cell Aug 30, 2004 Issued
Array ( [id] => 7081847 [patent_doc_number] => 20050047227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor device and ID generator configured as semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/924735 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047227.pdf [firstpage_image] =>[orig_patent_app_number] => 10924735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/924735
Semiconductor device and ID generator configured as semiconductor device Aug 23, 2004 Abandoned
Array ( [id] => 763718 [patent_doc_number] => 07012841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-14 [patent_title] => 'Circuit and method for current pulse compensation' [patent_app_type] => utility [patent_app_number] => 10/924631 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012841.pdf [firstpage_image] =>[orig_patent_app_number] => 10924631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/924631
Circuit and method for current pulse compensation Aug 23, 2004 Issued
Array ( [id] => 7081841 [patent_doc_number] => 20050047221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation' [patent_app_type] => utility [patent_app_number] => 10/923729 [patent_app_country] => US [patent_app_date] => 2004-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3348 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047221.pdf [firstpage_image] =>[orig_patent_app_number] => 10923729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923729
Negative drop voltage generator in semiconductor memory device and method of controlling negative voltage generation Aug 23, 2004 Issued
Array ( [id] => 5589781 [patent_doc_number] => 20060039232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Read command triggered synchronization circuitry' [patent_app_type] => utility [patent_app_number] => 10/922429 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039232.pdf [firstpage_image] =>[orig_patent_app_number] => 10922429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922429
Read command triggered synchronization circuitry Aug 18, 2004 Issued
Array ( [id] => 969858 [patent_doc_number] => 06940752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/920161 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 68 [patent_no_of_words] => 45167 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940752.pdf [firstpage_image] =>[orig_patent_app_number] => 10920161 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920161
Nonvolatile semiconductor memory device Aug 17, 2004 Issued
Array ( [id] => 644092 [patent_doc_number] => 07123508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Reference cells for TCCT based memory cells' [patent_app_type] => utility [patent_app_number] => 10/919956 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6571 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123508.pdf [firstpage_image] =>[orig_patent_app_number] => 10919956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/919956
Reference cells for TCCT based memory cells Aug 16, 2004 Issued
Array ( [id] => 7121330 [patent_doc_number] => 20050013159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/917320 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9304 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013159.pdf [firstpage_image] =>[orig_patent_app_number] => 10917320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917320
Semiconductor integrated circuit device Aug 12, 2004 Issued
Array ( [id] => 977276 [patent_doc_number] => 06934176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Systems for programmable memory using silicided poly-silicon fuses' [patent_app_type] => utility [patent_app_number] => 10/916606 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12509 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934176.pdf [firstpage_image] =>[orig_patent_app_number] => 10916606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916606
Systems for programmable memory using silicided poly-silicon fuses Aug 11, 2004 Issued
Array ( [id] => 652193 [patent_doc_number] => 07113416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Associative memory apparatus for searching data in which manhattan distance is minimum' [patent_app_type] => utility [patent_app_number] => 10/915430 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5464 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113416.pdf [firstpage_image] =>[orig_patent_app_number] => 10915430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915430
Associative memory apparatus for searching data in which manhattan distance is minimum Aug 10, 2004 Issued
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