Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7087736 [patent_doc_number] => 20050007848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method and system for using dynamic random access memory as cache memory' [patent_app_type] => utility [patent_app_number] => 10/912929 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4565 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007848.pdf [firstpage_image] =>[orig_patent_app_number] => 10912929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912929
Method and system for using dynamic random access memory as cache memory Aug 4, 2004 Issued
Array ( [id] => 7621640 [patent_doc_number] => 06977861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/911515 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8724 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977861.pdf [firstpage_image] =>[orig_patent_app_number] => 10911515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911515
Nonvolatile semiconductor memory device Aug 4, 2004 Issued
Array ( [id] => 957030 [patent_doc_number] => 06956784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Writable memory' [patent_app_type] => utility [patent_app_number] => 10/910231 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/956/06956784.pdf [firstpage_image] =>[orig_patent_app_number] => 10910231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910231
Writable memory Aug 2, 2004 Issued
Array ( [id] => 7126217 [patent_doc_number] => 20050057961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Semiconductor memory device providing redundancy' [patent_app_type] => utility [patent_app_number] => 10/911233 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2399 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057961.pdf [firstpage_image] =>[orig_patent_app_number] => 10911233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911233
Semiconductor memory device providing redundancy Aug 2, 2004 Issued
Array ( [id] => 947203 [patent_doc_number] => 06965538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Programming and evaluating through PMOS injection' [patent_app_type] => utility [patent_app_number] => 10/910201 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2635 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965538.pdf [firstpage_image] =>[orig_patent_app_number] => 10910201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910201
Programming and evaluating through PMOS injection Aug 2, 2004 Issued
Array ( [id] => 763711 [patent_doc_number] => 07012837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Method for erasing/programming a non-volatile electrically erasable memory' [patent_app_type] => utility [patent_app_number] => 10/903927 [patent_app_country] => US [patent_app_date] => 2004-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012837.pdf [firstpage_image] =>[orig_patent_app_number] => 10903927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/903927
Method for erasing/programming a non-volatile electrically erasable memory Jul 30, 2004 Issued
Array ( [id] => 991638 [patent_doc_number] => 06920079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Semiconductor device and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/902133 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9939 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920079.pdf [firstpage_image] =>[orig_patent_app_number] => 10902133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/902133
Semiconductor device and semiconductor memory device Jul 29, 2004 Issued
Array ( [id] => 1051680 [patent_doc_number] => 06862225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Buffer for a split cache line access' [patent_app_type] => utility [patent_app_number] => 10/897869 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3136 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862225.pdf [firstpage_image] =>[orig_patent_app_number] => 10897869 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897869
Buffer for a split cache line access Jul 22, 2004 Issued
Array ( [id] => 704672 [patent_doc_number] => 07064979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => utility [patent_app_number] => 10/897084 [patent_app_country] => US [patent_app_date] => 2004-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 25210 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064979.pdf [firstpage_image] =>[orig_patent_app_number] => 10897084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897084
Non-volatile semiconductor memory device and data programming method Jul 20, 2004 Issued
Array ( [id] => 7415625 [patent_doc_number] => 20040264271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => new [patent_app_number] => 10/892289 [patent_app_country] => US [patent_app_date] => 2004-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14741 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20040264271.pdf [firstpage_image] =>[orig_patent_app_number] => 10892289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/892289
Non-volatile semiconductor memory Jul 15, 2004 Issued
Array ( [id] => 745597 [patent_doc_number] => 07031204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Low power register apparatus having a two-way gating structure and method thereof' [patent_app_type] => utility [patent_app_number] => 10/891131 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3610 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031204.pdf [firstpage_image] =>[orig_patent_app_number] => 10891131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891131
Low power register apparatus having a two-way gating structure and method thereof Jul 14, 2004 Issued
Array ( [id] => 7036152 [patent_doc_number] => 20050033901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method and circuit for reading data from a ferroelectric memory cell' [patent_app_type] => utility [patent_app_number] => 10/882687 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033901.pdf [firstpage_image] =>[orig_patent_app_number] => 10882687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882687
Method and circuit for reading data from a ferroelectric memory cell Jul 1, 2004 Issued
Array ( [id] => 7616125 [patent_doc_number] => 06947319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Increased sensitivity in local probe of magnetic properties' [patent_app_type] => utility [patent_app_number] => 10/880276 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4918 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/947/06947319.pdf [firstpage_image] =>[orig_patent_app_number] => 10880276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880276
Increased sensitivity in local probe of magnetic properties Jun 29, 2004 Issued
Array ( [id] => 7257231 [patent_doc_number] => 20040240286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Method of preparing to test a capacitor' [patent_app_type] => new [patent_app_number] => 10/883415 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7463 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240286.pdf [firstpage_image] =>[orig_patent_app_number] => 10883415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883415
Method of preparing to test a capacitor Jun 29, 2004 Issued
Array ( [id] => 942202 [patent_doc_number] => 06970372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Dual gated finfet gain cell' [patent_app_type] => utility [patent_app_number] => 10/879833 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 62 [patent_no_of_words] => 8046 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970372.pdf [firstpage_image] =>[orig_patent_app_number] => 10879833 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/879833
Dual gated finfet gain cell Jun 28, 2004 Issued
Array ( [id] => 6965109 [patent_doc_number] => 20050232006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 10/873929 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 27396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20050232006.pdf [firstpage_image] =>[orig_patent_app_number] => 10873929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873929
Magnetic random access memory Jun 22, 2004 Issued
Array ( [id] => 7044423 [patent_doc_number] => 20050249018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Multi-port memory device' [patent_app_type] => utility [patent_app_number] => 10/876231 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9536 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20050249018.pdf [firstpage_image] =>[orig_patent_app_number] => 10876231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876231
Multi-port memory device Jun 22, 2004 Issued
Array ( [id] => 944808 [patent_doc_number] => 06967864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Semiconductor memory device including magneto resistive element and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/866129 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967864.pdf [firstpage_image] =>[orig_patent_app_number] => 10866129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866129
Semiconductor memory device including magneto resistive element and method of fabricating the same Jun 13, 2004 Issued
Array ( [id] => 7315846 [patent_doc_number] => 20040223382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Magnetic memory' [patent_app_type] => new [patent_app_number] => 10/864522 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13636 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20040223382.pdf [firstpage_image] =>[orig_patent_app_number] => 10864522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/864522
Magnetic memory Jun 9, 2004 Issued
Array ( [id] => 7604358 [patent_doc_number] => 07116577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping' [patent_app_type] => utility [patent_app_number] => 10/863529 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 21133 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116577.pdf [firstpage_image] =>[orig_patent_app_number] => 10863529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863529
Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping Jun 8, 2004 Issued
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