Gerald Mcclain

Array ( [id] => 7433969 [patent_doc_number] => 20040008558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Refresh control circuit and methods of operation and control of the refresh control circuit' [patent_app_type] => new [patent_app_number] => 10/421739 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3366 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20040008558.pdf [firstpage_image] =>[orig_patent_app_number] => 10421739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547269 [patent_doc_number] => 07177179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Magnetic memory, and its operating method' [patent_app_type] => utility [patent_app_number] => 10/512545 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 16416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177179.pdf [firstpage_image] =>[orig_patent_app_number] => 10512545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7418748 [patent_doc_number] => 20040208035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Data storage device with cable connector that can be securely positioned on a surface of the device' [patent_app_type] => new [patent_app_number] => 10/418939 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1309 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20040208035.pdf [firstpage_image] =>[orig_patent_app_number] => 10418939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1140166 [patent_doc_number] => 06785166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => B2 [patent_app_number] => 10/414344 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 25133 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 703 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785166.pdf [firstpage_image] =>[orig_patent_app_number] => 10414344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185325 [patent_doc_number] => 06738293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => B1 [patent_app_number] => 10/413826 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 0 [patent_no_of_words] => 25153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738293.pdf [firstpage_image] =>[orig_patent_app_number] => 10413826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 714051 [patent_doc_number] => 07057965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/512031 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6270 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057965.pdf [firstpage_image] =>[orig_patent_app_number] => 10512031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7178527 [patent_doc_number] => 20040202026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'HIGH SPEED LATCH AND COMPARE FUNCTION' [patent_app_type] => new [patent_app_number] => 10/413615 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1158 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20040202026.pdf [firstpage_image] =>[orig_patent_app_number] => 10413615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7195337 [patent_doc_number] => 20040085796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'System-in-package type semiconductor device' [patent_app_type] => new [patent_app_number] => 10/411271 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8479 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20040085796.pdf [firstpage_image] =>[orig_patent_app_number] => 10411271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7376768 [patent_doc_number] => 20040081012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Semiconductor memory device invalidating improper control command' [patent_app_type] => new [patent_app_number] => 10/408575 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 16654 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20040081012.pdf [firstpage_image] =>[orig_patent_app_number] => 10408575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1099265 [patent_doc_number] => 06822887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Semiconductor circuit device with mitigated load on interconnection line' [patent_app_type] => B2 [patent_app_number] => 10/406461 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7190 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822887.pdf [firstpage_image] =>[orig_patent_app_number] => 10406461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1054752 [patent_doc_number] => 06859395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages' [patent_app_type] => utility [patent_app_number] => 10/405233 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 61 [patent_no_of_words] => 18137 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859395.pdf [firstpage_image] =>[orig_patent_app_number] => 10405233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1108170 [patent_doc_number] => 06813193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Memory device and method of outputting data from a memory device' [patent_app_type] => B2 [patent_app_number] => 10/406019 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2118 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813193.pdf [firstpage_image] =>[orig_patent_app_number] => 10406019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1156125 [patent_doc_number] => 06775193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'System and method for testing multiple embedded memories' [patent_app_type] => B1 [patent_app_number] => 10/405265 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3716 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775193.pdf [firstpage_image] =>[orig_patent_app_number] => 10405265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1208616 [patent_doc_number] => 06717839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Bit-line shielding method for ferroelectric memories' [patent_app_type] => B1 [patent_app_number] => 10/404941 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3415 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717839.pdf [firstpage_image] =>[orig_patent_app_number] => 10404941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6622296 [patent_doc_number] => 20030210576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Programmable memory devices with latching buffer circuit and methods for operating the same' [patent_app_type] => new [patent_app_number] => 10/403739 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6182 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20030210576.pdf [firstpage_image] =>[orig_patent_app_number] => 10403739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1067391 [patent_doc_number] => 06847558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Integrated circuit and method of reading data from a memory device' [patent_app_type] => utility [patent_app_number] => 10/402743 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3336 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847558.pdf [firstpage_image] =>[orig_patent_app_number] => 10402743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180344 [patent_doc_number] => 06751154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/400043 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751154.pdf [firstpage_image] =>[orig_patent_app_number] => 10400043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1219912 [patent_doc_number] => 06707704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Semiconductor memory device and drive method therefor' [patent_app_type] => B2 [patent_app_number] => 10/392843 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10906 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707704.pdf [firstpage_image] =>[orig_patent_app_number] => 10392843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7627358 [patent_doc_number] => 06807083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => B2 [patent_app_number] => 10/393439 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807083.pdf [firstpage_image] =>[orig_patent_app_number] => 10393439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1003703 [patent_doc_number] => 06909642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Self trimming voltage generator' [patent_app_type] => utility [patent_app_number] => 10/387435 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2731 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/909/06909642.pdf [firstpage_image] =>[orig_patent_app_number] => 10387435 [rel_patent_id] =>[rel_patent_doc_number] =>)