Search

Gerald Mcclain

Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )

Most Active Art Unit
3652
Art Unit(s)
3653, 3652
Total Applications
1263
Issued Applications
964
Pending Applications
88
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1156191 [patent_doc_number] => 06775201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method and apparatus for outputting burst read data' [patent_app_type] => B2 [patent_app_number] => 10/299267 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4890 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775201.pdf [firstpage_image] =>[orig_patent_app_number] => 10299267 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299267
Method and apparatus for outputting burst read data Nov 18, 2002 Issued
Array ( [id] => 7624500 [patent_doc_number] => 06724676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Soft error improvement for latches' [patent_app_type] => B1 [patent_app_number] => 10/299037 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4668 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724676.pdf [firstpage_image] =>[orig_patent_app_number] => 10299037 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299037
Soft error improvement for latches Nov 17, 2002 Issued
Array ( [id] => 1155962 [patent_doc_number] => 06775173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Matrix-addressable apparatus with one or more memory devices' [patent_app_type] => B2 [patent_app_number] => 10/293341 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 6340 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775173.pdf [firstpage_image] =>[orig_patent_app_number] => 10293341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293341
Matrix-addressable apparatus with one or more memory devices Nov 13, 2002 Issued
Array ( [id] => 6681965 [patent_doc_number] => 20030117829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Circuit device having a fuse' [patent_app_type] => new [patent_app_number] => 10/293923 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11689 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117829.pdf [firstpage_image] =>[orig_patent_app_number] => 10293923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293923
Circuit device having a fuse Nov 12, 2002 Issued
Array ( [id] => 6719652 [patent_doc_number] => 20030053340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'DDR sdram for stable read operation' [patent_app_type] => new [patent_app_number] => 10/283535 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2751 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053340.pdf [firstpage_image] =>[orig_patent_app_number] => 10283535 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283535
DDR SDRAM for stable read operation Oct 28, 2002 Issued
Array ( [id] => 6695720 [patent_doc_number] => 20030107914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Magnetic random access memory' [patent_app_type] => new [patent_app_number] => 10/277735 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4446 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107914.pdf [firstpage_image] =>[orig_patent_app_number] => 10277735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/277735
Magnetic random access memory Oct 22, 2002 Issued
Array ( [id] => 1269031 [patent_doc_number] => 06661736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Apparatus and method for distributing a clock signal on a large scale integrated circuit' [patent_app_type] => B2 [patent_app_number] => 10/278197 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4657 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661736.pdf [firstpage_image] =>[orig_patent_app_number] => 10278197 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278197
Apparatus and method for distributing a clock signal on a large scale integrated circuit Oct 21, 2002 Issued
Array ( [id] => 6687336 [patent_doc_number] => 20030031059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/272998 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031059.pdf [firstpage_image] =>[orig_patent_app_number] => 10272998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/272998
Semiconductor integrated circuit device Oct 17, 2002 Issued
Array ( [id] => 1234528 [patent_doc_number] => 06693840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Non-volatile semiconductor memory device with enhanced erase/write cycle endurance' [patent_app_type] => B2 [patent_app_number] => 10/271139 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4955 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693840.pdf [firstpage_image] =>[orig_patent_app_number] => 10271139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271139
Non-volatile semiconductor memory device with enhanced erase/write cycle endurance Oct 14, 2002 Issued
Array ( [id] => 6687326 [patent_doc_number] => 20030031049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics' [patent_app_type] => new [patent_app_number] => 10/265100 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 86 [patent_no_of_words] => 28579 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031049.pdf [firstpage_image] =>[orig_patent_app_number] => 10265100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265100
Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics Oct 6, 2002 Issued
Array ( [id] => 1314918 [patent_doc_number] => 06618288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics' [patent_app_type] => B2 [patent_app_number] => 10/265106 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 101 [patent_no_of_words] => 28708 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618288.pdf [firstpage_image] =>[orig_patent_app_number] => 10265106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265106
Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics Oct 6, 2002 Issued
Array ( [id] => 1319810 [patent_doc_number] => 06611464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics' [patent_app_type] => B2 [patent_app_number] => 10/265233 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 104 [patent_no_of_words] => 28405 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611464.pdf [firstpage_image] =>[orig_patent_app_number] => 10265233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265233
Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics Oct 6, 2002 Issued
Array ( [id] => 1216103 [patent_doc_number] => 06711059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Memory controller' [patent_app_type] => B2 [patent_app_number] => 10/260135 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9703 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711059.pdf [firstpage_image] =>[orig_patent_app_number] => 10260135 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/260135
Memory controller Sep 26, 2002 Issued
Array ( [id] => 1268984 [patent_doc_number] => 06661727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Dynamic register with low clock rate testing capability' [patent_app_type] => B2 [patent_app_number] => 10/252491 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7271 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661727.pdf [firstpage_image] =>[orig_patent_app_number] => 10252491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252491
Dynamic register with low clock rate testing capability Sep 22, 2002 Issued
Array ( [id] => 1334722 [patent_doc_number] => 06600687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method of compensating for a defect within a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/253844 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7382 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600687.pdf [firstpage_image] =>[orig_patent_app_number] => 10253844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253844
Method of compensating for a defect within a semiconductor device Sep 22, 2002 Issued
Array ( [id] => 6649312 [patent_doc_number] => 20030076117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method and circuit for reading data from a ferroelectric memory cell' [patent_app_type] => new [patent_app_number] => 10/247375 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10935 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20030076117.pdf [firstpage_image] =>[orig_patent_app_number] => 10247375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247375
Method and circuit for reading data from a ferroelectric memory cell Sep 19, 2002 Issued
Array ( [id] => 1256049 [patent_doc_number] => 06671203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Nonvolatile semiconductor memory having page mode with a plurality of banks' [patent_app_type] => B2 [patent_app_number] => 10/233133 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 165 [patent_no_of_words] => 13756 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671203.pdf [firstpage_image] =>[orig_patent_app_number] => 10233133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233133
Nonvolatile semiconductor memory having page mode with a plurality of banks Aug 29, 2002 Issued
Array ( [id] => 1280759 [patent_doc_number] => 06650585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Leakage detection in programming algorithm for a flash memory device' [patent_app_type] => B2 [patent_app_number] => 10/232216 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6315 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650585.pdf [firstpage_image] =>[orig_patent_app_number] => 10232216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232216
Leakage detection in programming algorithm for a flash memory device Aug 28, 2002 Issued
Array ( [id] => 6644149 [patent_doc_number] => 20030007401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Leakage detection in programming algorithm for a flash memory device' [patent_app_type] => new [patent_app_number] => 10/231398 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6362 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007401.pdf [firstpage_image] =>[orig_patent_app_number] => 10231398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231398
Leakage detection in programming algorithm for a flash memory device Aug 28, 2002 Issued
Array ( [id] => 6681996 [patent_doc_number] => 20030117860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Flash memory with multiple status reading capability' [patent_app_type] => new [patent_app_number] => 10/225596 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 14974 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117860.pdf [firstpage_image] =>[orig_patent_app_number] => 10225596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225596
Flash memory with multiple status reading capability Aug 21, 2002 Issued
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