
Gerald Mcclain
Examiner (ID: 7690, Phone: (571)272-7803 , Office: P/3652 )
| Most Active Art Unit | 3652 |
| Art Unit(s) | 3653, 3652 |
| Total Applications | 1263 |
| Issued Applications | 964 |
| Pending Applications | 88 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1319749
[patent_doc_number] => 06611456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Method and apparatus for reducing the number of programmed bits in a memory array'
[patent_app_type] => B2
[patent_app_number] => 09/898725
[patent_app_country] => US
[patent_app_date] => 2001-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3162
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/611/06611456.pdf
[firstpage_image] =>[orig_patent_app_number] => 09898725
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/898725 | Method and apparatus for reducing the number of programmed bits in a memory array | Jul 2, 2001 | Issued |
Array
(
[id] => 6139720
[patent_doc_number] => 20020001241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Redundancy memory circuit'
[patent_app_type] => new
[patent_app_number] => 09/892935
[patent_app_country] => US
[patent_app_date] => 2001-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2358
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20020001241.pdf
[firstpage_image] =>[orig_patent_app_number] => 09892935
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/892935 | Redundancy memory circuit | Jun 26, 2001 | Issued |
Array
(
[id] => 1555920
[patent_doc_number] => 06349053
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Spin dependent tunneling memory'
[patent_app_type] => B1
[patent_app_number] => 09/891619
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 20577
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/349/06349053.pdf
[firstpage_image] =>[orig_patent_app_number] => 09891619
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/891619 | Spin dependent tunneling memory | Jun 25, 2001 | Issued |
Array
(
[id] => 1504371
[patent_doc_number] => 06487130
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => B2
[patent_app_number] => 09/885928
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 6355
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/487/06487130.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885928
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885928 | Semiconductor integrated circuit device | Jun 21, 2001 | Issued |
Array
(
[id] => 1470089
[patent_doc_number] => 06459651
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Semiconductor memory device having data masking pin and memory system including the same'
[patent_app_type] => B1
[patent_app_number] => 09/886718
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3296
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459651.pdf
[firstpage_image] =>[orig_patent_app_number] => 09886718
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886718 | Semiconductor memory device having data masking pin and memory system including the same | Jun 20, 2001 | Issued |
Array
(
[id] => 1349967
[patent_doc_number] => 06590800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-08
[patent_title] => 'Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL'
[patent_app_type] => B2
[patent_app_number] => 09/882617
[patent_app_country] => US
[patent_app_date] => 2001-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 30
[patent_no_of_words] => 8747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/590/06590800.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882617
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882617 | Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL | Jun 14, 2001 | Issued |
Array
(
[id] => 1442992
[patent_doc_number] => 06335880
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-01-01
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => B2
[patent_app_number] => 09/881020
[patent_app_country] => US
[patent_app_date] => 2001-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 29
[patent_no_of_words] => 13960
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/335/06335880.pdf
[firstpage_image] =>[orig_patent_app_number] => 09881020
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/881020 | Nonvolatile semiconductor memory | Jun 14, 2001 | Issued |
Array
(
[id] => 7077853
[patent_doc_number] => 20010040822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/880934
[patent_app_country] => US
[patent_app_date] => 2001-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14092
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20010040822.pdf
[firstpage_image] =>[orig_patent_app_number] => 09880934
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/880934 | Nonvolatile semiconductor memory | Jun 14, 2001 | Issued |
Array
(
[id] => 6321016
[patent_doc_number] => 20020196664
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'BIASING CIRCUIT FOR MULTI-LEVEL MEMORY CELLS'
[patent_app_type] => new
[patent_app_number] => 09/882535
[patent_app_country] => US
[patent_app_date] => 2001-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6176
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20020196664.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882535
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882535 | Sensing circuit for memory cells | Jun 13, 2001 | Issued |
Array
(
[id] => 1457792
[patent_doc_number] => 06462991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-08
[patent_title] => 'Method of erasing data stored in a nonvolatile memory'
[patent_app_type] => B2
[patent_app_number] => 09/878915
[patent_app_country] => US
[patent_app_date] => 2001-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 3376
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/462/06462991.pdf
[firstpage_image] =>[orig_patent_app_number] => 09878915
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/878915 | Method of erasing data stored in a nonvolatile memory | Jun 12, 2001 | Issued |
Array
(
[id] => 6395568
[patent_doc_number] => 20020181266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'STEERING GATE AND BIT LINE SEGMENTATION IN NON-VOLATILE MEMORIES'
[patent_app_type] => new
[patent_app_number] => 09/871333
[patent_app_country] => US
[patent_app_date] => 2001-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4715
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20020181266.pdf
[firstpage_image] =>[orig_patent_app_number] => 09871333
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871333 | Steering gate and bit line segmentation in non-volatile memories | May 30, 2001 | Issued |
Array
(
[id] => 7064219
[patent_doc_number] => 20010043505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-22
[patent_title] => 'Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same'
[patent_app_type] => new
[patent_app_number] => 09/862833
[patent_app_country] => US
[patent_app_date] => 2001-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4837
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20010043505.pdf
[firstpage_image] =>[orig_patent_app_number] => 09862833
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/862833 | Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same | May 21, 2001 | Issued |
Array
(
[id] => 6223018
[patent_doc_number] => 20020003722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/860613
[patent_app_country] => US
[patent_app_date] => 2001-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 23339
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20020003722.pdf
[firstpage_image] =>[orig_patent_app_number] => 09860613
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/860613 | Nonvolatile semiconductor memory | May 20, 2001 | Issued |
| 09/806223 | METHOD AND DEVICE FOR WRITING AND READING A BUFFER MEMORY | May 20, 2001 | Abandoned |
Array
(
[id] => 6207269
[patent_doc_number] => 20020071330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/860429
[patent_app_country] => US
[patent_app_date] => 2001-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8542
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20020071330.pdf
[firstpage_image] =>[orig_patent_app_number] => 09860429
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/860429 | Semiconductor device | May 20, 2001 | Issued |
Array
(
[id] => 1552269
[patent_doc_number] => 06347056
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Recording of result information in a built-in self-test circuit and method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/859333
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5748
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/347/06347056.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859333
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859333 | Recording of result information in a built-in self-test circuit and method therefor | May 15, 2001 | Issued |
Array
(
[id] => 6094286
[patent_doc_number] => 20020051375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-02
[patent_title] => 'Memory card system'
[patent_app_type] => new
[patent_app_number] => 09/851335
[patent_app_country] => US
[patent_app_date] => 2001-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1677
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20020051375.pdf
[firstpage_image] =>[orig_patent_app_number] => 09851335
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/851335 | Memory module system | May 8, 2001 | Issued |
Array
(
[id] => 1396024
[patent_doc_number] => 06560140
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-06
[patent_title] => 'Single ended two-stage memory cell'
[patent_app_type] => B2
[patent_app_number] => 09/852427
[patent_app_country] => US
[patent_app_date] => 2001-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3396
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/560/06560140.pdf
[firstpage_image] =>[orig_patent_app_number] => 09852427
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/852427 | Single ended two-stage memory cell | May 8, 2001 | Issued |
Array
(
[id] => 1473323
[patent_doc_number] => 06407956
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-06-18
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 09/849882
[patent_app_country] => US
[patent_app_date] => 2001-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 52
[patent_no_of_words] => 11289
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/407/06407956.pdf
[firstpage_image] =>[orig_patent_app_number] => 09849882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/849882 | Semiconductor memory device | May 3, 2001 | Issued |
Array
(
[id] => 6886233
[patent_doc_number] => 20010019502
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-06
[patent_title] => 'Semiconductor integrated circuit device having hierarchical power source arrangement'
[patent_app_type] => new
[patent_app_number] => 09/846223
[patent_app_country] => US
[patent_app_date] => 2001-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 52
[patent_no_of_words] => 50831
[patent_no_of_claims] => 73
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20010019502.pdf
[firstpage_image] =>[orig_patent_app_number] => 09846223
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/846223 | Semiconductor integrated circuit device having hierarchical power source arrangement | May 1, 2001 | Issued |