Search

Gerald P Tolin

Examiner (ID: 17702)

Most Active Art Unit
2103
Art Unit(s)
3201, 2835, 2504, 2103, 2105, 2104, 2107, 3621, 2899
Total Applications
2170
Issued Applications
1900
Pending Applications
26
Abandoned Applications
244

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18925238 [patent_doc_number] => 20240028242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SCRUB RATE CONTROL FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/229539 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229539
SCRUB RATE CONTROL FOR A MEMORY DEVICE Aug 1, 2023 Pending
Array ( [id] => 18789058 [patent_doc_number] => 20230377671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/362934 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362934
METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT Jul 30, 2023 Pending
Array ( [id] => 18651631 [patent_doc_number] => 20230297467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => ERROR DETECTION AND CHECKING IN WIRELESS COMMUNICATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/201558 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201558
ERROR DETECTION AND CHECKING IN WIRELESS COMMUNICATION SYSTEMS May 23, 2023 Pending
Array ( [id] => 18600797 [patent_doc_number] => 20230275600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 18/314938 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314938
PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME May 9, 2023 Pending
Array ( [id] => 18599059 [patent_doc_number] => 20230273859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => STORAGE SYSTEM SPANNING MULTIPLE FAILURE DOMAINS [patent_app_type] => utility [patent_app_number] => 18/314861 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314861
STORAGE SYSTEM SPANNING MULTIPLE FAILURE DOMAINS May 9, 2023 Pending
Array ( [id] => 18677916 [patent_doc_number] => 20230315563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Energy-Efficient Error-Correction-Detection Storage [patent_app_type] => utility [patent_app_number] => 18/306542 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306542
Energy-Efficient Error-Correction-Detection Storage Apr 24, 2023 Pending
Array ( [id] => 18730152 [patent_doc_number] => 20230344450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => QUASI-CYCLIC LDPC CODING AND DECODING METHOD AND APPARATUS, AND LDPC CODER AND DECODER [patent_app_type] => utility [patent_app_number] => 18/138702 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138702
QUASI-CYCLIC LDPC CODING AND DECODING METHOD AND APPARATUS, AND LDPC CODER AND DECODER Apr 23, 2023 Pending
Array ( [id] => 18654032 [patent_doc_number] => 20230299877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF [patent_app_type] => utility [patent_app_number] => 18/304029 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304029
Transmitter and method for generating additional parity thereof Apr 19, 2023 Issued
Array ( [id] => 19212221 [patent_doc_number] => 12001283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Energy efficient storage of error-correction-detection information [patent_app_type] => utility [patent_app_number] => 18/130810 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18130810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/130810
Energy efficient storage of error-correction-detection information Apr 3, 2023 Issued
Array ( [id] => 18571447 [patent_doc_number] => 20230261784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => TECHNIQUES FOR PRE AND POST FORWARD ERROR CORRECTION AND PACKET PADDING IN RADIO TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/189878 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189878
TECHNIQUES FOR PRE AND POST FORWARD ERROR CORRECTION AND PACKET PADDING IN RADIO TRANSMISSION Mar 23, 2023 Pending
Array ( [id] => 18740989 [patent_doc_number] => 20230349969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/186549 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186549
Processing system, related integrated circuit, device and method Mar 19, 2023 Issued
Array ( [id] => 18501139 [patent_doc_number] => 20230223956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => METHOD AND APPARATUS FOR ENCODING POLAR CODE, AND METHOD AND APPARATUS FOR DECODING POLAR CODE [patent_app_type] => utility [patent_app_number] => 18/183272 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/183272
METHOD AND APPARATUS FOR ENCODING POLAR CODE, AND METHOD AND APPARATUS FOR DECODING POLAR CODE Mar 13, 2023 Pending
Array ( [id] => 18863396 [patent_doc_number] => 20230417832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => TRAINING METHOD AND TEST APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/158181 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158181
TRAINING METHOD AND TEST APPARATUS USING THE SAME Jan 22, 2023 Pending
Array ( [id] => 18380633 [patent_doc_number] => 20230155723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF [patent_app_type] => utility [patent_app_number] => 18/155645 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155645
Transmitter and method for generating additional parity thereof Jan 16, 2023 Issued
Array ( [id] => 18899442 [patent_doc_number] => 20240014927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => PHYSICAL CODING SUBLAYER WITH MODIFIED BIT ORDERING TO IMPROVE ERROR BURST RESILIENCY [patent_app_type] => utility [patent_app_number] => 18/085698 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085698 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085698
PHYSICAL CODING SUBLAYER WITH MODIFIED BIT ORDERING TO IMPROVE ERROR BURST RESILIENCY Dec 20, 2022 Pending
Array ( [id] => 18312522 [patent_doc_number] => 20230116422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MEMORY, MEMORY SYSTEM, OPERATION METHOD OF THE MEMORY, AND OPERATION OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/077795 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077795
MEMORY, MEMORY SYSTEM, OPERATION METHOD OF THE MEMORY, AND OPERATION OF THE MEMORY SYSTEM Dec 7, 2022 Pending
Array ( [id] => 19017024 [patent_doc_number] => 11923973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Method and apparatus for encoding data using a polar code [patent_app_type] => utility [patent_app_number] => 17/962023 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 21207 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962023
Method and apparatus for encoding data using a polar code Oct 6, 2022 Issued
Array ( [id] => 18951551 [patent_doc_number] => 11894861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Parallel bit interleaver [patent_app_type] => utility [patent_app_number] => 17/959570 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 52 [patent_no_of_words] => 15189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959570
Parallel bit interleaver Oct 3, 2022 Issued
Array ( [id] => 18163542 [patent_doc_number] => 20230030135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => DATA PROCESSING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/955173 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955173
DATA PROCESSING METHOD AND APPARATUS Sep 27, 2022 Pending
Array ( [id] => 18607893 [patent_doc_number] => 11749369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Memory device architecture coupled to a system-on-chip [patent_app_type] => utility [patent_app_number] => 17/943156 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943156
Memory device architecture coupled to a system-on-chip Sep 11, 2022 Issued
Menu