
Gerald R. Ewoldt
Examiner (ID: 11995, Phone: (571)272-0843 , Office: P/1644 )
| Most Active Art Unit | 1644 |
| Art Unit(s) | 1644 |
| Total Applications | 1060 |
| Issued Applications | 256 |
| Pending Applications | 142 |
| Abandoned Applications | 661 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12717268
[patent_doc_number] => 20180130922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => MONOCRYSTAL AND POLYCRYSTAL TEXTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 15/866756
[patent_app_country] => US
[patent_app_date] => 2018-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4086
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 406
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866756
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/866756 | Monocrystal and polycrystal texturing method | Jan 9, 2018 | Issued |
Array
(
[id] => 14492075
[patent_doc_number] => 10332838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-25
[patent_title] => Schemes for forming barrier layers for copper in interconnect structures
[patent_app_type] => utility
[patent_app_number] => 15/860014
[patent_app_country] => US
[patent_app_date] => 2018-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5262
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860014
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/860014 | Schemes for forming barrier layers for copper in interconnect structures | Jan 1, 2018 | Issued |
Array
(
[id] => 13862105
[patent_doc_number] => 10192777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Method of fabricating STI trench
[patent_app_type] => utility
[patent_app_number] => 15/854765
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2822
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854765
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854765 | Method of fabricating STI trench | Dec 26, 2017 | Issued |
Array
(
[id] => 12896443
[patent_doc_number] => 20180190656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-05
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/854827
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2949
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854827
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854827 | Method of manufacturing a semiconductor device | Dec 26, 2017 | Issued |
Array
(
[id] => 12873286
[patent_doc_number] => 20180182937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => METHOD OF MANUFACTURING LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/854517
[patent_app_country] => US
[patent_app_date] => 2017-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9225
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854517
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854517 | Method of manufacturing light emitting device | Dec 25, 2017 | Issued |
Array
(
[id] => 13528239
[patent_doc_number] => 20180315662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/854311
[patent_app_country] => US
[patent_app_date] => 2017-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5810
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854311
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854311 | Semiconductor device and method of manufacturing the same | Dec 25, 2017 | Issued |
Array
(
[id] => 14769057
[patent_doc_number] => 10395930
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Substrate treating apparatus and substrate treating method
[patent_app_type] => utility
[patent_app_number] => 15/854198
[patent_app_country] => US
[patent_app_date] => 2017-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5874
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854198
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854198 | Substrate treating apparatus and substrate treating method | Dec 25, 2017 | Issued |
Array
(
[id] => 12873247
[patent_doc_number] => 20180182924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/854289
[patent_app_country] => US
[patent_app_date] => 2017-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4847
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854289
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854289 | Method of manufacturing light-emitting device | Dec 25, 2017 | Issued |
Array
(
[id] => 13306595
[patent_doc_number] => 20180204834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-19
[patent_title] => APPROACH TO FABRICATION OF AN ON-CHIP RESISTOR WITH A FIELD EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 15/846887
[patent_app_country] => US
[patent_app_date] => 2017-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846887
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/846887 | Approach to fabrication of an on-chip resistor with a field effect transistor | Dec 18, 2017 | Issued |
Array
(
[id] => 14367369
[patent_doc_number] => 10304999
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Light-emitting devices
[patent_app_type] => utility
[patent_app_number] => 15/846773
[patent_app_country] => US
[patent_app_date] => 2017-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4016
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846773
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/846773 | Light-emitting devices | Dec 18, 2017 | Issued |
Array
(
[id] => 12615201
[patent_doc_number] => 20180096897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => METHOD OF FABRICATING DMOS AND CMOS TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 15/831897
[patent_app_country] => US
[patent_app_date] => 2017-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10537
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831897
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/831897 | Method of fabricating DMOS and CMOS transistors | Dec 4, 2017 | Issued |
Array
(
[id] => 13293191
[patent_doc_number] => 10157796
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-12-18
[patent_title] => Forming of marking trenches in structure for multiple patterning lithography
[patent_app_type] => utility
[patent_app_number] => 15/811953
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 28
[patent_no_of_words] => 6342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811953
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811953 | Forming of marking trenches in structure for multiple patterning lithography | Nov 13, 2017 | Issued |
Array
(
[id] => 12849205
[patent_doc_number] => 20180174908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => MANUFACTURING PROCESS OF ELEMENT CHIP
[patent_app_type] => utility
[patent_app_number] => 15/811733
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7013
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811733
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811733 | Manufacturing process of element chip | Nov 13, 2017 | Issued |
Array
(
[id] => 14644261
[patent_doc_number] => 10366879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-30
[patent_title] => Dry and wet etch resistance for atomic layer deposited TiO2 for SIT spacer application
[patent_app_type] => utility
[patent_app_number] => 15/811872
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3866
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811872
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811872 | Dry and wet etch resistance for atomic layer deposited TiO2 for SIT spacer application | Nov 13, 2017 | Issued |
Array
(
[id] => 14268101
[patent_doc_number] => 10283623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Integrated circuits with gate stacks
[patent_app_type] => utility
[patent_app_number] => 15/812350
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 27
[patent_no_of_words] => 8821
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812350
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/812350 | Integrated circuits with gate stacks | Nov 13, 2017 | Issued |
Array
(
[id] => 14205051
[patent_doc_number] => 10269647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Self-aligned EPI contact flow
[patent_app_type] => utility
[patent_app_number] => 15/811188
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3068
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811188
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811188 | Self-aligned EPI contact flow | Nov 12, 2017 | Issued |
Array
(
[id] => 14317075
[patent_doc_number] => 20190148241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/810831
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6308
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810831
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/810831 | Fin field effect transistor (FinFET) device structure and method for forming the same | Nov 12, 2017 | Issued |
Array
(
[id] => 14316891
[patent_doc_number] => 20190148149
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => TECHNIQUE AND RELATED SEMICONDUCTOR DEVICES BASED ON CRYSTALLINE SEMICONDUCTOR MATERIAL FORMED ON THE BASIS OF DEPOSITED AMORPHOUS SEMICONDUCTOR MATERIAL
[patent_app_type] => utility
[patent_app_number] => 15/810638
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10232
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810638
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/810638 | Technique and related semiconductor devices based on crystalline semiconductor material formed on the basis of deposited amorphous semiconductor material | Nov 12, 2017 | Issued |
Array
(
[id] => 14460265
[patent_doc_number] => 10326108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Display panel and repairing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/811657
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 5119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811657
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811657 | Display panel and repairing method thereof | Nov 12, 2017 | Issued |
Array
(
[id] => 13485603
[patent_doc_number] => 20180294344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-11
[patent_title] => METHOD FOR MANUFACTURING LOW-TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, LOW-TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/809673
[patent_app_country] => US
[patent_app_date] => 2017-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7083
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809673
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/809673 | Method for manufacturing low-temperature poly-silicon thin film transistor, low-temperature poly-silicon thin film transistor and display device | Nov 9, 2017 | Issued |