Search

Gerald R. Ewoldt

Examiner (ID: 11995, Phone: (571)272-0843 , Office: P/1644 )

Most Active Art Unit
1644
Art Unit(s)
1644
Total Applications
1060
Issued Applications
256
Pending Applications
142
Abandoned Applications
661

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10016057 [patent_doc_number] => 09059079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Processing of insulators and semiconductors' [patent_app_type] => utility [patent_app_number] => 14/036925 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6781 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036925
Processing of insulators and semiconductors Sep 24, 2013 Issued
Array ( [id] => 9491146 [patent_doc_number] => 20140141553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP' [patent_app_type] => utility [patent_app_number] => 14/035958 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/035958
METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP Sep 24, 2013 Abandoned
Array ( [id] => 10876213 [patent_doc_number] => 08900999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Low temperature high pressure high H2/WF6 ratio W process for 3D NAND application' [patent_app_type] => utility [patent_app_number] => 14/036157 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3174 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036157
Low temperature high pressure high H2/WF6 ratio W process for 3D NAND application Sep 24, 2013 Issued
Array ( [id] => 9384045 [patent_doc_number] => 20140087527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'METHOD OF FORMING THIN FILM POLY SILICON LAYER AND METHOD OF FORMING THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/035930 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4638 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035930 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/035930
METHOD OF FORMING THIN FILM POLY SILICON LAYER AND METHOD OF FORMING THIN FILM TRANSISTOR Sep 23, 2013 Abandoned
Array ( [id] => 9983543 [patent_doc_number] => 09029250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Method for producing semiconductor regions including impurities' [patent_app_type] => utility [patent_app_number] => 14/035185 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 7178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14035185 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/035185
Method for producing semiconductor regions including impurities Sep 23, 2013 Issued
Array ( [id] => 11564755 [patent_doc_number] => 09627349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Method for applying a bonding layer' [patent_app_type] => utility [patent_app_number] => 14/909157 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 10689 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14909157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/909157
Method for applying a bonding layer Sep 12, 2013 Issued
Array ( [id] => 9893277 [patent_doc_number] => 20150048476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/024102 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4237 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024102
Semiconductor devices and methods of manufacture Sep 10, 2013 Issued
Array ( [id] => 9937203 [patent_doc_number] => 08987008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Integrated circuit layout and method with double patterning' [patent_app_type] => utility [patent_app_number] => 13/971363 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 8025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971363 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971363
Integrated circuit layout and method with double patterning Aug 19, 2013 Issued
Array ( [id] => 10926324 [patent_doc_number] => 20140329345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY' [patent_app_type] => utility [patent_app_number] => 13/971407 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971407 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971407
Manufacturing method of organic light emitting diode display Aug 19, 2013 Issued
Array ( [id] => 9195227 [patent_doc_number] => 20130334542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/970586 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11674 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970586 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/970586
Power JFET Aug 18, 2013 Issued
Array ( [id] => 10892833 [patent_doc_number] => 08916445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'Semiconductor devices and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 13/969017 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969017
Semiconductor devices and methods of manufacture Aug 15, 2013 Issued
Array ( [id] => 10850907 [patent_doc_number] => 08877585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-04 [patent_title] => 'Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration' [patent_app_type] => utility [patent_app_number] => 13/969180 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969180 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969180
Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration Aug 15, 2013 Issued
Array ( [id] => 9869119 [patent_doc_number] => 08956890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Method for producing group III nitride semiconductor light-emitting device' [patent_app_type] => utility [patent_app_number] => 13/968295 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13968295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/968295
Method for producing group III nitride semiconductor light-emitting device Aug 14, 2013 Issued
Array ( [id] => 10870186 [patent_doc_number] => 08895381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures' [patent_app_type] => utility [patent_app_number] => 13/967994 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 13666 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967994
Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures Aug 14, 2013 Issued
Array ( [id] => 10498884 [patent_doc_number] => 09227274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-05 [patent_title] => 'Joining via nano-scale reinforced bonding media: materials, procedures and applications thereof' [patent_app_type] => utility [patent_app_number] => 13/963197 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3570 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963197
Joining via nano-scale reinforced bonding media: materials, procedures and applications thereof Aug 8, 2013 Issued
Array ( [id] => 9171581 [patent_doc_number] => 20130313566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'GaN Epitaxy With Migration Enhancement and Surface Energy Modification' [patent_app_type] => utility [patent_app_number] => 13/957380 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13957380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/957380
GaN Epitaxy With Migration Enhancement and Surface Energy Modification Jul 31, 2013 Abandoned
Array ( [id] => 9171661 [patent_doc_number] => 20130313646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Structure and Method for Fabricating Fin Devices' [patent_app_type] => utility [patent_app_number] => 13/957108 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 7101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13957108 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/957108
Structure and method for fabricating fin devices Jul 31, 2013 Issued
Array ( [id] => 9922790 [patent_doc_number] => 08980752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Method of forming a plurality of spaced features' [patent_app_type] => utility [patent_app_number] => 13/948050 [patent_app_country] => US [patent_app_date] => 2013-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/948050
Method of forming a plurality of spaced features Jul 21, 2013 Issued
Array ( [id] => 10898731 [patent_doc_number] => 08921953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Method for MEMS device fabrication and device formed' [patent_app_type] => utility [patent_app_number] => 13/946479 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4587 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946479 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946479
Method for MEMS device fabrication and device formed Jul 18, 2013 Issued
Array ( [id] => 9171691 [patent_doc_number] => 20130313676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/924730 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5159 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924730
Method of manufacturing semiconductor devices Jun 23, 2013 Issued
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