Search

Gerard T. Higgins

Examiner (ID: 18981)

Most Active Art Unit
1785
Art Unit(s)
1785, 1796, 1759, 4174, 1794
Total Applications
1018
Issued Applications
552
Pending Applications
98
Abandoned Applications
380

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9013812 [patent_doc_number] => 20130228776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/855203 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8490 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855203 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855203
Semiconductor device including gate and conductor electrodes Apr 1, 2013 Issued
Array ( [id] => 8963621 [patent_doc_number] => 20130203223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/833891 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12176 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833891
Method of manufacturing semiconductor device with offset sidewall structure Mar 14, 2013 Issued
Array ( [id] => 9778607 [patent_doc_number] => 08853815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains' [patent_app_type] => utility [patent_app_number] => 13/831360 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6042 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831360 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831360
Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains Mar 13, 2013 Issued
Array ( [id] => 9542324 [patent_doc_number] => 20140166971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/795872 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2758 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795872 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795872
Variable resistance memory device with shunt gate connected to corresponding gate Mar 11, 2013 Issued
Array ( [id] => 9038214 [patent_doc_number] => 20130240852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'Light-Emitting Device and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/796703 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12095 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796703
Manufacturing method of light-emitting device with nano-imprinting wiring Mar 11, 2013 Issued
Array ( [id] => 9360511 [patent_doc_number] => 20140070383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Pre-Molded MEMS Device Package with Conductive Shell' [patent_app_type] => utility [patent_app_number] => 13/795902 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5954 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795902
MEMS device package with conductive shell Mar 11, 2013 Issued
Array ( [id] => 9059764 [patent_doc_number] => 08546199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Method of manufacturing transparent transistor with multi-layered structures' [patent_app_type] => utility [patent_app_number] => 13/792436 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 3651 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792436
Method of manufacturing transparent transistor with multi-layered structures Mar 10, 2013 Issued
Array ( [id] => 10876840 [patent_doc_number] => 08901631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Vertical transistor in semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/792231 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2088 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792231 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792231
Vertical transistor in semiconductor device and method for fabricating the same Mar 10, 2013 Issued
Array ( [id] => 9059763 [patent_doc_number] => 08546198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Method of manufacturing transparent transistor with multi-layered structures' [patent_app_type] => utility [patent_app_number] => 13/792395 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 3649 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792395 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792395
Method of manufacturing transparent transistor with multi-layered structures Mar 10, 2013 Issued
Array ( [id] => 8928025 [patent_doc_number] => 20130183785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING CHIP HAVING BUFFER LAYER WITH NITRIDE SEMICONDUCOR IN CARBON NANO TUBE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/787758 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2213 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787758 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787758
Method for manufacturing light emitting chip having buffer layer with nitride semiconductor in carbon nano tube structure Mar 5, 2013 Issued
Array ( [id] => 9827723 [patent_doc_number] => 08936951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Method of manufacturing semiconductor lasers' [patent_app_type] => utility [patent_app_number] => 13/776428 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 4271 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776428 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776428
Method of manufacturing semiconductor lasers Feb 24, 2013 Issued
Array ( [id] => 9802785 [patent_doc_number] => 20150014730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'LIGHT-EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 14/380085 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2223 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14380085 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/380085
LIGHT-EMITTING DIODE Feb 21, 2013 Abandoned
Array ( [id] => 9038389 [patent_doc_number] => 20130241027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING ISOLATION REGION' [patent_app_type] => utility [patent_app_number] => 13/772775 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13772775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/772775
Semiconductor device having isolation region Feb 20, 2013 Issued
Array ( [id] => 9654213 [patent_doc_number] => 20140225218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/765080 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765080 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765080
ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS Feb 11, 2013 Abandoned
Array ( [id] => 9552863 [patent_doc_number] => 08759914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'Deep sub-micron interconnection circuitry with shielded layer structure' [patent_app_type] => utility [patent_app_number] => 13/762813 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5041 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762813
Deep sub-micron interconnection circuitry with shielded layer structure Feb 7, 2013 Issued
Array ( [id] => 9750272 [patent_doc_number] => 08841754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Semiconductor devices with stress relief layers' [patent_app_type] => utility [patent_app_number] => 13/763309 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 15432 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763309 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763309
Semiconductor devices with stress relief layers Feb 7, 2013 Issued
Array ( [id] => 9663030 [patent_doc_number] => 08810014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Semiconductor package including conductive member disposed between the heat dissipation member and the lead frame' [patent_app_type] => utility [patent_app_number] => 13/761750 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4111 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761750 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761750
Semiconductor package including conductive member disposed between the heat dissipation member and the lead frame Feb 6, 2013 Issued
Array ( [id] => 9059794 [patent_doc_number] => 08546229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Methods for fabricating bipolar transistors with improved gain' [patent_app_type] => utility [patent_app_number] => 13/760882 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 10245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760882 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760882
Methods for fabricating bipolar transistors with improved gain Feb 5, 2013 Issued
Array ( [id] => 9763043 [patent_doc_number] => 08847371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Electronic component module including a lead frame and an insulating resin having a thickness less than or equal to a thickness of the lead frame and method for producing same' [patent_app_type] => utility [patent_app_number] => 13/758131 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 8604 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758131
Electronic component module including a lead frame and an insulating resin having a thickness less than or equal to a thickness of the lead frame and method for producing same Feb 3, 2013 Issued
Array ( [id] => 10035564 [patent_doc_number] => 09076891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer' [patent_app_type] => utility [patent_app_number] => 13/754513 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754513
Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer Jan 29, 2013 Issued
Menu