Search

Gerard T. Higgins

Examiner (ID: 18981)

Most Active Art Unit
1785
Art Unit(s)
1785, 1796, 1759, 4174, 1794
Total Applications
1018
Issued Applications
552
Pending Applications
98
Abandoned Applications
380

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10199074 [patent_doc_number] => 20150084060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/464220 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2291 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464220
Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate Aug 19, 2014 Issued
Array ( [id] => 9898803 [patent_doc_number] => 20150054002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/464570 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4410 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464570
Semiconductor structure with sensor chip and landing pads Aug 19, 2014 Issued
Array ( [id] => 9928450 [patent_doc_number] => 20150076642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'PHOTODETECTION DEVICE AND SENSOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/464020 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6797 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464020
Photodetection device and sensor package Aug 19, 2014 Issued
Array ( [id] => 9905766 [patent_doc_number] => 20150060966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'IMAGE SENSORS WITH SILICIDE LIGHT SHIELDS' [patent_app_type] => utility [patent_app_number] => 14/464408 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464408 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464408
IMAGE SENSORS WITH SILICIDE LIGHT SHIELDS Aug 19, 2014 Abandoned
Array ( [id] => 10151826 [patent_doc_number] => 09184123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-10 [patent_title] => 'Package substrate with current flow shaping features' [patent_app_type] => utility [patent_app_number] => 14/464591 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464591 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464591
Package substrate with current flow shaping features Aug 19, 2014 Issued
Array ( [id] => 10946440 [patent_doc_number] => 20140349461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'METHOD FOR USING METAL BILAYER' [patent_app_type] => utility [patent_app_number] => 14/458263 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2660 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458263
METHOD FOR USING METAL BILAYER Aug 12, 2014 Abandoned
Array ( [id] => 10422336 [patent_doc_number] => 20150307347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SYSTEM ON A CHIP USING INTEGRATED MEMS AND CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 14/445012 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10468 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14445012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/445012
System on a chip using integrated MEMS and CMOS devices Jul 27, 2014 Issued
Array ( [id] => 10929886 [patent_doc_number] => 20140332907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/337683 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3524 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337683
Semiconductor device with an aluminum alloy gate Jul 21, 2014 Issued
Array ( [id] => 10929899 [patent_doc_number] => 20140332920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'SHALLOW TRENCH ISOLATION' [patent_app_type] => utility [patent_app_number] => 14/337170 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3578 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337170
Shallow trench isolation Jul 20, 2014 Issued
Array ( [id] => 10919872 [patent_doc_number] => 20140322891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'METHOD OF FORMING SHALLOW TRENCH ISOLATIONS' [patent_app_type] => utility [patent_app_number] => 14/329982 [patent_app_country] => US [patent_app_date] => 2014-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3523 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329982
Method of forming shallow trench isolations Jul 12, 2014 Issued
Array ( [id] => 10912347 [patent_doc_number] => 20140315364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'Methods Of Forming A Vertical Transistor' [patent_app_type] => utility [patent_app_number] => 14/319201 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319201
Methods of forming a vertical transistor Jun 29, 2014 Issued
Array ( [id] => 11681471 [patent_doc_number] => 09680006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Silicon carbide semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/907023 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 9112 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14907023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/907023
Silicon carbide semiconductor device and method of manufacturing the same Jun 16, 2014 Issued
Array ( [id] => 10041941 [patent_doc_number] => 09082654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Method of manufacturing non-volatile memory cell with simplified step of forming floating gate' [patent_app_type] => utility [patent_app_number] => 14/290138 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 112 [patent_figures_cnt] => 223 [patent_no_of_words] => 21724 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/290138
Method of manufacturing non-volatile memory cell with simplified step of forming floating gate May 28, 2014 Issued
Array ( [id] => 9699070 [patent_doc_number] => 20140248755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES' [patent_app_type] => utility [patent_app_number] => 14/279786 [patent_app_country] => US [patent_app_date] => 2014-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7767 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279786
Methods of fabricating nonvolatile memory devices including voids between active regions and related devices May 15, 2014 Issued
Array ( [id] => 10047473 [patent_doc_number] => 09087879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level' [patent_app_type] => utility [patent_app_number] => 14/268606 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5984 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268606
Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level May 1, 2014 Issued
Array ( [id] => 9983486 [patent_doc_number] => 09029194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Making an integrated circuit module with dual leadframes' [patent_app_type] => utility [patent_app_number] => 14/267565 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2464 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267565
Making an integrated circuit module with dual leadframes Apr 30, 2014 Issued
Array ( [id] => 9682601 [patent_doc_number] => 20140239364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'MOS Varactor Optimized Layout and Methods' [patent_app_type] => utility [patent_app_number] => 14/263744 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14263744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/263744
MOS varactor optimized layout and methods Apr 27, 2014 Issued
Array ( [id] => 11432079 [patent_doc_number] => 09570404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application' [patent_app_type] => utility [patent_app_number] => 14/242851 [patent_app_country] => US [patent_app_date] => 2014-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 3913 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/242851
Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application Mar 31, 2014 Issued
Array ( [id] => 11489387 [patent_doc_number] => 09595460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Substrate processing apparatus, recording medium and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/781074 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 21140 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14781074 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/781074
Substrate processing apparatus, recording medium and method of manufacturing semiconductor device Mar 25, 2014 Issued
Array ( [id] => 9753943 [patent_doc_number] => 20140284643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'POWER SURFACE MOUNT LIGHT EMITTING DIE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/221982 [patent_app_country] => US [patent_app_date] => 2014-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6505 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14221982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/221982
POWER SURFACE MOUNT LIGHT EMITTING DIE PACKAGE Mar 20, 2014 Abandoned
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