
Getente A. Yimer
Examiner (ID: 10962, Phone: (571)270-7106 , Office: P/2181 )
| Most Active Art Unit | 2181 |
| Art Unit(s) | 2181 |
| Total Applications | 695 |
| Issued Applications | 582 |
| Pending Applications | 65 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18788037
[patent_doc_number] => 20230376434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => PLC In-band Control for Wearables and Hearables
[patent_app_type] => utility
[patent_app_number] => 18/042557
[patent_app_country] => US
[patent_app_date] => 2020-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5501
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18042557
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/042557 | PLC In-band Control for Wearables and Hearables | Aug 25, 2020 | Pending |
Array
(
[id] => 17325387
[patent_doc_number] => 11216399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Application processor for low power operation, electronic device including the same and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 16/998532
[patent_app_country] => US
[patent_app_date] => 2020-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8582
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998532
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/998532 | Application processor for low power operation, electronic device including the same and method of operating the same | Aug 19, 2020 | Issued |
Array
(
[id] => 19152452
[patent_doc_number] => 11977362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-07
[patent_title] => Control device and distributed control system
[patent_app_type] => utility
[patent_app_number] => 17/770416
[patent_app_country] => US
[patent_app_date] => 2020-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 14019
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17770416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/770416 | Control device and distributed control system | Aug 18, 2020 | Issued |
Array
(
[id] => 18276095
[patent_doc_number] => 11615039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Data transmission system
[patent_app_type] => utility
[patent_app_number] => 16/945693
[patent_app_country] => US
[patent_app_date] => 2020-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 11
[patent_no_of_words] => 11552
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945693
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/945693 | Data transmission system | Jul 30, 2020 | Issued |
Array
(
[id] => 17757254
[patent_doc_number] => 11397546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Memory system
[patent_app_type] => utility
[patent_app_number] => 16/942112
[patent_app_country] => US
[patent_app_date] => 2020-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11428
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942112
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/942112 | Memory system | Jul 28, 2020 | Issued |
Array
(
[id] => 17083993
[patent_doc_number] => 20210278999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-09
[patent_title] => MEMORY SYSTEM FOR ACCURATELY PREDICTING POWER REQUIRED FOR SEQUENTIAL COMMAND OPERATIONS PERFORMED IN MEMORY DEVICE, AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/939834
[patent_app_country] => US
[patent_app_date] => 2020-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27286
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939834
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/939834 | Memory system for accurately predicting power required for sequential command operations performed in memory device, and operation method thereof | Jul 26, 2020 | Issued |
Array
(
[id] => 17454892
[patent_doc_number] => 11269751
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Hierarchical evaluation of multivariate anomaly level
[patent_app_type] => utility
[patent_app_number] => 16/898457
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5589
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898457
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/898457 | Hierarchical evaluation of multivariate anomaly level | Jun 10, 2020 | Issued |
Array
(
[id] => 16691144
[patent_doc_number] => 20210073622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO SPIKING EVENTS, AND RELATED METHODS, SYSTEMS AND DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/887665
[patent_app_country] => US
[patent_app_date] => 2020-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14016
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887665
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/887665 | Performing processing-in-memory operations related to spiking events, and related methods, systems and devices | May 28, 2020 | Issued |
Array
(
[id] => 16470815
[patent_doc_number] => 20200372352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-26
[patent_title] => SYSTEM AND METHOD FOR MACHINE LEARNING ARCHITECTURE WITH VARIATIONAL HYPER-RNN
[patent_app_type] => utility
[patent_app_number] => 16/881768
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12708
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881768
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/881768 | System and method for machine learning architecture with variational hyper-RNN | May 21, 2020 | Issued |
Array
(
[id] => 18324750
[patent_doc_number] => 20230122878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => EXPANSION BASE UNIT, CONTROL DEVICE, CONTROL SYSTEM, AND CONTROL METHOD
[patent_app_type] => utility
[patent_app_number] => 17/917251
[patent_app_country] => US
[patent_app_date] => 2020-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7490
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17917251
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/917251 | Expansion base unit, control device, control system, and control method | May 18, 2020 | Issued |
Array
(
[id] => 16455122
[patent_doc_number] => 20200364548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => MEMRISTIVE NEURAL NETWORK COMPUTING ENGINE USING CMOS-COMPATIBLE CHARGE-TRAP-TRANSISTOR (CTT)
[patent_app_type] => utility
[patent_app_number] => 16/876063
[patent_app_country] => US
[patent_app_date] => 2020-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9808
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876063
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/876063 | Memristive neural network computing engine using CMOS-compatible charge-trap-transistor (CTT) | May 16, 2020 | Issued |
Array
(
[id] => 16849573
[patent_doc_number] => 20210150318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-20
[patent_title] => MEMORY DEVICE INCLUDING NEURAL NETWORK PROCESSING CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/868181
[patent_app_country] => US
[patent_app_date] => 2020-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14638
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868181
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/868181 | Memory device including neural network processing circuit | May 5, 2020 | Issued |
Array
(
[id] => 17201812
[patent_doc_number] => 20210341907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-04
[patent_title] => ETHERNET I/O CARD SCANNER
[patent_app_type] => utility
[patent_app_number] => 16/861567
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861567
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/861567 | Ethernet I/O card scanner | Apr 28, 2020 | Issued |
Array
(
[id] => 17172499
[patent_doc_number] => 20210326169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => SYSTEMS AND METHODS TO CONTROL BANDWIDTH THROUGH SHARED TRANSACTION LIMITS
[patent_app_type] => utility
[patent_app_number] => 16/852107
[patent_app_country] => US
[patent_app_date] => 2020-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6372
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852107
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/852107 | Systems and methods to control bandwidth through shared transaction limits | Apr 16, 2020 | Issued |
Array
(
[id] => 17223582
[patent_doc_number] => 11176083
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => Switching crossbar for graphics pipeline
[patent_app_type] => utility
[patent_app_number] => 16/847781
[patent_app_country] => US
[patent_app_date] => 2020-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 12471
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847781
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/847781 | Switching crossbar for graphics pipeline | Apr 13, 2020 | Issued |
Array
(
[id] => 18890099
[patent_doc_number] => 11868872
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-01-09
[patent_title] => Direct memory access operation for neural network accelerator
[patent_app_type] => utility
[patent_app_number] => 16/836493
[patent_app_country] => US
[patent_app_date] => 2020-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 17330
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836493
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/836493 | Direct memory access operation for neural network accelerator | Mar 30, 2020 | Issued |
Array
(
[id] => 16176099
[patent_doc_number] => 20200223067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => METHOD, DEVICE, AND PROGRAM FOR PROCESSING SIGNALS
[patent_app_type] => utility
[patent_app_number] => 16/831280
[patent_app_country] => US
[patent_app_date] => 2020-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5659
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831280
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/831280 | Method, device, and program for processing signals | Mar 25, 2020 | Issued |
Array
(
[id] => 16331314
[patent_doc_number] => 20200302280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => Hybrid Delta Modulator As Neuron With Memory
[patent_app_type] => utility
[patent_app_number] => 16/820704
[patent_app_country] => US
[patent_app_date] => 2020-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4532
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820704
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/820704 | Hybrid delta modulator as neuron with memory | Mar 15, 2020 | Issued |
Array
(
[id] => 17606024
[patent_doc_number] => 11334513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-17
[patent_title] => Data communication circuit
[patent_app_type] => utility
[patent_app_number] => 16/819681
[patent_app_country] => US
[patent_app_date] => 2020-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5688
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819681
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/819681 | Data communication circuit | Mar 15, 2020 | Issued |
Array
(
[id] => 16615597
[patent_doc_number] => 20210034250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/818047
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6366
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818047
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/818047 | Storage device | Mar 12, 2020 | Issued |