Search

Gims S. Philippe

Examiner (ID: 4263, Phone: (571)272-7336 , Office: P/2489 )

Most Active Art Unit
2424
Art Unit(s)
2621, 2424, 2713, 2489, 2485, 2613, 2482
Total Applications
1814
Issued Applications
1446
Pending Applications
162
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
19/147065 Method and Apparatus for Automatic Switching Between primary BIOS and backup BIOS, and Computer Jul 9, 2025 Pending
Array ( [id] => 19878283 [patent_doc_number] => 20250110540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT DEVICE HAVING MULTIPLE INITIALIZATION/POWER UP MODES [patent_app_type] => utility [patent_app_number] => 18/916160 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18916160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/916160
POWER MANAGEMENT INTEGRATED CIRCUIT DEVICE HAVING MULTIPLE INITIALIZATION/POWER UP MODES Oct 14, 2024 Pending
Array ( [id] => 20375611 [patent_doc_number] => 12483056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Charging system for prioritized power distribution and dynamic power adjustment [patent_app_type] => utility [patent_app_number] => 18/899243 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2302 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18899243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/899243
Charging system for prioritized power distribution and dynamic power adjustment Sep 26, 2024 Issued
Array ( [id] => 19685951 [patent_doc_number] => 20250004496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MULTI-PHASE SIGNAL GENERATION [patent_app_type] => utility [patent_app_number] => 18/884635 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/884635
MULTI-PHASE SIGNAL GENERATION Sep 12, 2024 Pending
Array ( [id] => 19833974 [patent_doc_number] => 20250085760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/826795 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826795
COMMUNICATION SYSTEM Sep 5, 2024 Pending
Array ( [id] => 19644690 [patent_doc_number] => 20240419210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES [patent_app_type] => utility [patent_app_number] => 18/819437 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819437
SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES Aug 28, 2024 Pending
Array ( [id] => 20395022 [patent_doc_number] => 20250370497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => CHIPLET CLOCK FORWARDING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/680368 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680368
CHIPLET CLOCK FORWARDING ARCHITECTURE May 30, 2024 Pending
Array ( [id] => 20365648 [patent_doc_number] => 20250355460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MULTI-PHASE CLOCK CALIBRATION IN A RECEIVER [patent_app_type] => utility [patent_app_number] => 18/667840 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667840
Multi-phase clock calibration in a receiver May 16, 2024 Issued
Array ( [id] => 19617075 [patent_doc_number] => 20240402755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => POWER MANAGEMENT BASED ON SELF-SYNCHRONIZATION OF CLOCKS [patent_app_type] => utility [patent_app_number] => 18/653846 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653846
POWER MANAGEMENT BASED ON SELF-SYNCHRONIZATION OF CLOCKS May 1, 2024 Pending
Array ( [id] => 20249564 [patent_doc_number] => 20250298433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => CLOCK AND DATA RECOVERY CIRCUIT MODULE, MEMORY STORAGE DEVICE AND SIGNAL CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 18/637397 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637397
Clock and data recovery circuit module, memory storage device and signal calibration method Apr 15, 2024 Issued
Array ( [id] => 19405416 [patent_doc_number] => 20240288927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DYNAMICALLY POWER ON/OFF PROCESSING CLUSTERS DURING EXECUTION [patent_app_type] => utility [patent_app_number] => 18/633932 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633932
DYNAMICALLY POWER ON/OFF PROCESSING CLUSTERS DURING EXECUTION Apr 11, 2024 Pending
Array ( [id] => 20296365 [patent_doc_number] => 20250321608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => LOCAL CLOCK DRIVEN DETUNE ON A CONTINUOUS CLOCK GRID [patent_app_type] => utility [patent_app_number] => 18/631284 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631284
LOCAL CLOCK DRIVEN DETUNE ON A CONTINUOUS CLOCK GRID Apr 9, 2024 Pending
Array ( [id] => 19779929 [patent_doc_number] => 12228961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory system using asymmetric source-synchronous clocking [patent_app_type] => utility [patent_app_number] => 18/629138 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 5788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629138
Memory system using asymmetric source-synchronous clocking Apr 7, 2024 Issued
Array ( [id] => 20284832 [patent_doc_number] => 20250310074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Environmental-based parameters optimization of clock [patent_app_type] => utility [patent_app_number] => 18/624169 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624169
Environmental-based parameters optimization of clock Apr 1, 2024 Pending
Array ( [id] => 20249563 [patent_doc_number] => 20250298432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TRANSMITTER-SIDE LINK TRAINING WITH IN-BAND HANDSHAKING [patent_app_type] => utility [patent_app_number] => 18/615238 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615238
TRANSMITTER-SIDE LINK TRAINING WITH IN-BAND HANDSHAKING Mar 24, 2024 Pending
Array ( [id] => 19481641 [patent_doc_number] => 20240329683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => NEURAL PROCESSOR, NEURAL PROCESSING DEVICE AND CLOCK GATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/612806 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612806
Neural processor, neural processing device and clock gating method thereof Mar 20, 2024 Issued
Array ( [id] => 20234084 [patent_doc_number] => 20250291403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => PROCESSORS HAVING CORE CONTROL CIRCUITS TO CONTROL CORE TRANSITIONS BETWEEN LOW POWER MODES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/607859 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607859
PROCESSORS HAVING CORE CONTROL CIRCUITS TO CONTROL CORE TRANSITIONS BETWEEN LOW POWER MODES AND RELATED METHODS Mar 17, 2024 Pending
Array ( [id] => 19481675 [patent_doc_number] => 20240329717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR DEVICE, TIME MEASUREMENT METHOD AND TIME MEASUREMENT PROGRAM [patent_app_type] => utility [patent_app_number] => 18/594672 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594672
SEMICONDUCTOR DEVICE, TIME MEASUREMENT METHOD AND TIME MEASUREMENT PROGRAM Mar 3, 2024 Pending
Array ( [id] => 20579940 [patent_doc_number] => 12572189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Customized thermal and power policies in computers [patent_app_type] => utility [patent_app_number] => 18/581216 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581216
Customized thermal and power policies in computers Feb 18, 2024 Issued
Array ( [id] => 19219620 [patent_doc_number] => 20240184324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => System and Method For Global Synchronization of Time in a Distributed Processing Environment [patent_app_type] => utility [patent_app_number] => 18/439189 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439189
System and method for global synchronization of time in a distributed processing environment Feb 11, 2024 Issued
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