Search

Ginette Peralta

Examiner (ID: 17098)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
09/314999 UTILIZATION OF SIH4 SOAK AND PURGE IN DEPOSITION PROCESSES May 18, 1999 Abandoned
Array ( [id] => 4354516 [patent_doc_number] => 06218298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Tungsten-filled deep trenches' [patent_app_type] => 1 [patent_app_number] => 9/315089 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 964 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218298.pdf [firstpage_image] =>[orig_patent_app_number] => 315089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315089
Tungsten-filled deep trenches May 18, 1999 Issued
Array ( [id] => 4381146 [patent_doc_number] => 06277703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method for manufacturing an SOI wafer' [patent_app_type] => 1 [patent_app_number] => 9/311889 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2254 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277703.pdf [firstpage_image] =>[orig_patent_app_number] => 311889 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311889
Method for manufacturing an SOI wafer May 13, 1999 Issued
Array ( [id] => 4408600 [patent_doc_number] => 06265301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures' [patent_app_type] => 1 [patent_app_number] => 9/310258 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265301.pdf [firstpage_image] =>[orig_patent_app_number] => 310258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310258
Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures May 11, 1999 Issued
Array ( [id] => 1175799 [patent_doc_number] => 06750495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Damascene capacitors for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/310388 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750495.pdf [firstpage_image] =>[orig_patent_app_number] => 09310388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310388
Damascene capacitors for integrated circuits May 11, 1999 Issued
Array ( [id] => 4155273 [patent_doc_number] => 06114214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for forming a high-density dram cell with a double-crown rugged polysilicon capacitor' [patent_app_type] => 1 [patent_app_number] => 9/310889 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114214.pdf [firstpage_image] =>[orig_patent_app_number] => 310889 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310889
Method for forming a high-density dram cell with a double-crown rugged polysilicon capacitor May 11, 1999 Issued
Array ( [id] => 4354138 [patent_doc_number] => 06218272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for fabricating conductive pad' [patent_app_type] => 1 [patent_app_number] => 9/307659 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4830 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218272.pdf [firstpage_image] =>[orig_patent_app_number] => 307659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307659
Method for fabricating conductive pad May 9, 1999 Issued
Array ( [id] => 4182732 [patent_doc_number] => 06150258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Plasma deposited fluorinated amorphous carbon films' [patent_app_type] => 1 [patent_app_number] => 9/303538 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3963 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150258.pdf [firstpage_image] =>[orig_patent_app_number] => 303538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303538
Plasma deposited fluorinated amorphous carbon films May 2, 1999 Issued
Array ( [id] => 1468519 [patent_doc_number] => 06459123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Double gated transistor' [patent_app_type] => B1 [patent_app_number] => 09/302768 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 6392 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459123.pdf [firstpage_image] =>[orig_patent_app_number] => 09302768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302768
Double gated transistor Apr 29, 1999 Issued
Array ( [id] => 4341533 [patent_doc_number] => 06284443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for image adjustment' [patent_app_type] => 1 [patent_app_number] => 9/302628 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3806 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284443.pdf [firstpage_image] =>[orig_patent_app_number] => 302628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302628
Method and apparatus for image adjustment Apr 29, 1999 Issued
Array ( [id] => 4285459 [patent_doc_number] => 06197110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Mass production of silicon dioxide film by liquid phase deposition method' [patent_app_type] => 1 [patent_app_number] => 9/302119 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197110.pdf [firstpage_image] =>[orig_patent_app_number] => 302119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302119
Mass production of silicon dioxide film by liquid phase deposition method Apr 28, 1999 Issued
Array ( [id] => 4287220 [patent_doc_number] => 06268288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Plasma treated thermal CVD of TaN films from tantalum halide precursors' [patent_app_type] => 1 [patent_app_number] => 9/300659 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6317 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268288.pdf [firstpage_image] =>[orig_patent_app_number] => 300659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300659
Plasma treated thermal CVD of TaN films from tantalum halide precursors Apr 26, 1999 Issued
Array ( [id] => 4408709 [patent_doc_number] => 06265311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'PECVD of TaN films from tantalum halide precursors' [patent_app_type] => 1 [patent_app_number] => 9/300658 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6587 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265311.pdf [firstpage_image] =>[orig_patent_app_number] => 300658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300658
PECVD of TaN films from tantalum halide precursors Apr 26, 1999 Issued
09/299969 METHOD FOR FORMING A NITRIDIZED INTERFACE ON A SEMICONDUCTOR SUBSTRATE Apr 25, 1999 Abandoned
Array ( [id] => 4357839 [patent_doc_number] => 06191017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method of forming a multi-layered dual-polysilicon structure' [patent_app_type] => 1 [patent_app_number] => 9/298068 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2303 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191017.pdf [firstpage_image] =>[orig_patent_app_number] => 298068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298068
Method of forming a multi-layered dual-polysilicon structure Apr 21, 1999 Issued
09/298928 RUGGED POLYSILICON CUP-SHAPED CAPACITOR Apr 21, 1999 Abandoned
Array ( [id] => 1495487 [patent_doc_number] => 06342723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Integrated circuit having temporary conductive path structure and method for forming the same' [patent_app_type] => B1 [patent_app_number] => 09/295988 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342723.pdf [firstpage_image] =>[orig_patent_app_number] => 09295988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295988
Integrated circuit having temporary conductive path structure and method for forming the same Apr 20, 1999 Issued
Array ( [id] => 1495487 [patent_doc_number] => 06342723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Integrated circuit having temporary conductive path structure and method for forming the same' [patent_app_type] => B1 [patent_app_number] => 09/295988 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342723.pdf [firstpage_image] =>[orig_patent_app_number] => 09295988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295988
Integrated circuit having temporary conductive path structure and method for forming the same Apr 20, 1999 Issued
Array ( [id] => 1495487 [patent_doc_number] => 06342723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Integrated circuit having temporary conductive path structure and method for forming the same' [patent_app_type] => B1 [patent_app_number] => 09/295988 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342723.pdf [firstpage_image] =>[orig_patent_app_number] => 09295988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295988
Integrated circuit having temporary conductive path structure and method for forming the same Apr 20, 1999 Issued
Array ( [id] => 1495487 [patent_doc_number] => 06342723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Integrated circuit having temporary conductive path structure and method for forming the same' [patent_app_type] => B1 [patent_app_number] => 09/295988 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342723.pdf [firstpage_image] =>[orig_patent_app_number] => 09295988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295988
Integrated circuit having temporary conductive path structure and method for forming the same Apr 20, 1999 Issued
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