Search

Ginette Peralta

Examiner (ID: 17098)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4195056 [patent_doc_number] => 06153919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Bipolar transistor with polysilicon dummy emitter' [patent_app_type] => 1 [patent_app_number] => 9/236619 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3711 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153919.pdf [firstpage_image] =>[orig_patent_app_number] => 236619 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236619
Bipolar transistor with polysilicon dummy emitter Jan 25, 1999 Issued
Array ( [id] => 4282258 [patent_doc_number] => 06281535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/236048 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 4592 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281535.pdf [firstpage_image] =>[orig_patent_app_number] => 236048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236048
Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell Jan 21, 1999 Issued
Array ( [id] => 1490286 [patent_doc_number] => 06417090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer' [patent_app_type] => B1 [patent_app_number] => 09/225008 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3193 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417090.pdf [firstpage_image] =>[orig_patent_app_number] => 09225008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225008
Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer Jan 3, 1999 Issued
Array ( [id] => 4388135 [patent_doc_number] => 06278163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'HV transistor structure and corresponding manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/224939 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 3008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278163.pdf [firstpage_image] =>[orig_patent_app_number] => 224939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224939
HV transistor structure and corresponding manufacturing method Dec 30, 1998 Issued
Array ( [id] => 1507365 [patent_doc_number] => 06440814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Electrostatic discharge protection for sensors' [patent_app_type] => B1 [patent_app_number] => 09/223629 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440814.pdf [firstpage_image] =>[orig_patent_app_number] => 09223629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223629
Electrostatic discharge protection for sensors Dec 29, 1998 Issued
Array ( [id] => 1550471 [patent_doc_number] => 06399487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method of reducing phase transition temperature by using silicon-germanium alloys' [patent_app_type] => B1 [patent_app_number] => 09/222269 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2241 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399487.pdf [firstpage_image] =>[orig_patent_app_number] => 09222269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222269
Method of reducing phase transition temperature by using silicon-germanium alloys Dec 27, 1998 Issued
Array ( [id] => 4276948 [patent_doc_number] => 06246087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory cell structure for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/217988 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 3368 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246087.pdf [firstpage_image] =>[orig_patent_app_number] => 217988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217988
Memory cell structure for semiconductor memory device Dec 21, 1998 Issued
Array ( [id] => 4095468 [patent_doc_number] => 06096661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for depositing silicon dioxide using low temperatures' [patent_app_type] => 1 [patent_app_number] => 9/212198 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3325 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096661.pdf [firstpage_image] =>[orig_patent_app_number] => 212198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212198
Method for depositing silicon dioxide using low temperatures Dec 14, 1998 Issued
Array ( [id] => 4419805 [patent_doc_number] => 06177349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Preventing Cu dendrite formation and growth' [patent_app_type] => 1 [patent_app_number] => 9/206169 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177349.pdf [firstpage_image] =>[orig_patent_app_number] => 206169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206169
Preventing Cu dendrite formation and growth Dec 6, 1998 Issued
Array ( [id] => 4204976 [patent_doc_number] => 06077761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for fabricating a transistor gate with a T-like structure' [patent_app_type] => 1 [patent_app_number] => 9/206178 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2478 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077761.pdf [firstpage_image] =>[orig_patent_app_number] => 206178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206178
Method for fabricating a transistor gate with a T-like structure Dec 3, 1998 Issued
Array ( [id] => 4236339 [patent_doc_number] => 06143669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method of growing gate oxides' [patent_app_type] => 1 [patent_app_number] => 9/192498 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1892 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143669.pdf [firstpage_image] =>[orig_patent_app_number] => 192498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192498
Method of growing gate oxides Nov 16, 1998 Issued
Array ( [id] => 4294220 [patent_doc_number] => 06211561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Interconnect structure and method employing air gaps between metal lines and between metal layers' [patent_app_type] => 1 [patent_app_number] => 9/193499 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 39 [patent_no_of_words] => 7042 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211561.pdf [firstpage_image] =>[orig_patent_app_number] => 193499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193499
Interconnect structure and method employing air gaps between metal lines and between metal layers Nov 15, 1998 Issued
Array ( [id] => 4222163 [patent_doc_number] => 06010938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method for making a load resistor on a semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 9/192018 [patent_app_country] => US [patent_app_date] => 1998-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1305 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010938.pdf [firstpage_image] =>[orig_patent_app_number] => 192018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192018
Method for making a load resistor on a semiconductor chip Nov 10, 1998 Issued
Array ( [id] => 1412741 [patent_doc_number] => 06524954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Reduction of tungsten silicide resistivity by boron ion implantation' [patent_app_type] => B1 [patent_app_number] => 09/188758 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2633 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524954.pdf [firstpage_image] =>[orig_patent_app_number] => 09188758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188758
Reduction of tungsten silicide resistivity by boron ion implantation Nov 8, 1998 Issued
Array ( [id] => 4359436 [patent_doc_number] => 06169039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Electron bean curing of low-k dielectrics in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/187169 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2782 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169039.pdf [firstpage_image] =>[orig_patent_app_number] => 187169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187169
Electron bean curing of low-k dielectrics in integrated circuits Nov 5, 1998 Issued
Array ( [id] => 4100463 [patent_doc_number] => 06066574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Hot plate cure process for BCB low k interlevel dielectric' [patent_app_type] => 1 [patent_app_number] => 9/187429 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066574.pdf [firstpage_image] =>[orig_patent_app_number] => 187429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187429
Hot plate cure process for BCB low k interlevel dielectric Nov 5, 1998 Issued
Array ( [id] => 793169 [patent_doc_number] => 06982215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'N type impurity doping using implantation of P2+ ions or As2+ Ions' [patent_app_type] => utility [patent_app_number] => 09/186388 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2055 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982215.pdf [firstpage_image] =>[orig_patent_app_number] => 09186388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186388
N type impurity doping using implantation of P2+ ions or As2+ Ions Nov 4, 1998 Issued
Array ( [id] => 4408606 [patent_doc_number] => 06309969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Copper metallization structure and method of construction' [patent_app_type] => 1 [patent_app_number] => 9/184579 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4276 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309969.pdf [firstpage_image] =>[orig_patent_app_number] => 184579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184579
Copper metallization structure and method of construction Nov 2, 1998 Issued
Array ( [id] => 4395447 [patent_doc_number] => 06297153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of manufacturing barrier metal film of semiconductor device and method of manufacturing metal interconnection film of semiconductor device using the same' [patent_app_type] => 1 [patent_app_number] => 9/185089 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4071 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297153.pdf [firstpage_image] =>[orig_patent_app_number] => 185089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185089
Method of manufacturing barrier metal film of semiconductor device and method of manufacturing metal interconnection film of semiconductor device using the same Nov 2, 1998 Issued
Array ( [id] => 4031356 [patent_doc_number] => 05963832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Removal of metal cusp for improved contact fill' [patent_app_type] => 1 [patent_app_number] => 9/184489 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5255 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963832.pdf [firstpage_image] =>[orig_patent_app_number] => 184489 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184489
Removal of metal cusp for improved contact fill Nov 1, 1998 Issued
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