
Ginette Peralta
Examiner (ID: 17098)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4195056
[patent_doc_number] => 06153919
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Bipolar transistor with polysilicon dummy emitter'
[patent_app_type] => 1
[patent_app_number] => 9/236619
[patent_app_country] => US
[patent_app_date] => 1999-01-26
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[pdf_file] => patents/06/153/06153919.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/236619 | Bipolar transistor with polysilicon dummy emitter | Jan 25, 1999 | Issued |
Array
(
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[patent_doc_number] => 06281535
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[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell'
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[patent_app_number] => 9/236048
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[patent_app_date] => 1999-01-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/236048 | Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell | Jan 21, 1999 | Issued |
Array
(
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[patent_doc_number] => 06417090
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[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer'
[patent_app_type] => B1
[patent_app_number] => 09/225008
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[patent_app_date] => 1999-01-04
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[firstpage_image] =>[orig_patent_app_number] => 09225008
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225008 | Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer | Jan 3, 1999 | Issued |
Array
(
[id] => 4388135
[patent_doc_number] => 06278163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'HV transistor structure and corresponding manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/224939
[patent_app_country] => US
[patent_app_date] => 1998-12-31
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[firstpage_image] =>[orig_patent_app_number] => 224939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/224939 | HV transistor structure and corresponding manufacturing method | Dec 30, 1998 | Issued |
Array
(
[id] => 1507365
[patent_doc_number] => 06440814
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[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Electrostatic discharge protection for sensors'
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[patent_app_number] => 09/223629
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/223629 | Electrostatic discharge protection for sensors | Dec 29, 1998 | Issued |
Array
(
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[patent_doc_number] => 06399487
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[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method of reducing phase transition temperature by using silicon-germanium alloys'
[patent_app_type] => B1
[patent_app_number] => 09/222269
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[firstpage_image] =>[orig_patent_app_number] => 09222269
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222269 | Method of reducing phase transition temperature by using silicon-germanium alloys | Dec 27, 1998 | Issued |
Array
(
[id] => 4276948
[patent_doc_number] => 06246087
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[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Memory cell structure for semiconductor memory device'
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[patent_app_number] => 9/217988
[patent_app_country] => US
[patent_app_date] => 1998-12-22
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[firstpage_image] =>[orig_patent_app_number] => 217988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/217988 | Memory cell structure for semiconductor memory device | Dec 21, 1998 | Issued |
Array
(
[id] => 4095468
[patent_doc_number] => 06096661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method for depositing silicon dioxide using low temperatures'
[patent_app_type] => 1
[patent_app_number] => 9/212198
[patent_app_country] => US
[patent_app_date] => 1998-12-15
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[pdf_file] => patents/06/096/06096661.pdf
[firstpage_image] =>[orig_patent_app_number] => 212198
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212198 | Method for depositing silicon dioxide using low temperatures | Dec 14, 1998 | Issued |
Array
(
[id] => 4419805
[patent_doc_number] => 06177349
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Preventing Cu dendrite formation and growth'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 206169
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206169 | Preventing Cu dendrite formation and growth | Dec 6, 1998 | Issued |
Array
(
[id] => 4204976
[patent_doc_number] => 06077761
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[patent_issue_date] => 2000-06-20
[patent_title] => 'Method for fabricating a transistor gate with a T-like structure'
[patent_app_type] => 1
[patent_app_number] => 9/206178
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[firstpage_image] =>[orig_patent_app_number] => 206178
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206178 | Method for fabricating a transistor gate with a T-like structure | Dec 3, 1998 | Issued |
Array
(
[id] => 4236339
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[patent_issue_date] => 2000-11-07
[patent_title] => 'Method of growing gate oxides'
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[firstpage_image] =>[orig_patent_app_number] => 192498
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/192498 | Method of growing gate oxides | Nov 16, 1998 | Issued |
Array
(
[id] => 4294220
[patent_doc_number] => 06211561
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[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Interconnect structure and method employing air gaps between metal lines and between metal layers'
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[firstpage_image] =>[orig_patent_app_number] => 193499
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/193499 | Interconnect structure and method employing air gaps between metal lines and between metal layers | Nov 15, 1998 | Issued |
Array
(
[id] => 4222163
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[patent_title] => 'Method for making a load resistor on a semiconductor chip'
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[firstpage_image] =>[orig_patent_app_number] => 192018
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/192018 | Method for making a load resistor on a semiconductor chip | Nov 10, 1998 | Issued |
Array
(
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[patent_title] => 'Reduction of tungsten silicide resistivity by boron ion implantation'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187169 | Electron bean curing of low-k dielectrics in integrated circuits | Nov 5, 1998 | Issued |
Array
(
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[patent_title] => 'Hot plate cure process for BCB low k interlevel dielectric'
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Array
(
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[patent_title] => 'N type impurity doping using implantation of P2+ ions or As2+ Ions'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/184489 | Removal of metal cusp for improved contact fill | Nov 1, 1998 | Issued |