
Ginette Peralta
Examiner (ID: 17098)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4309416
[patent_doc_number] => 06188098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/178620
[patent_app_country] => US
[patent_app_date] => 1998-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 28
[patent_no_of_words] => 5694
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188098.pdf
[firstpage_image] =>[orig_patent_app_number] => 178620
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178620 | Semiconductor device and method of manufacturing the same | Oct 25, 1998 | Issued |
Array
(
[id] => 4333727
[patent_doc_number] => 06320242
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Semiconductor device having trimmable fuses and position alignment marker formed of thin film'
[patent_app_type] => 1
[patent_app_number] => 9/176339
[patent_app_country] => US
[patent_app_date] => 1998-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 46
[patent_no_of_words] => 9151
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/320/06320242.pdf
[firstpage_image] =>[orig_patent_app_number] => 176339
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176339 | Semiconductor device having trimmable fuses and position alignment marker formed of thin film | Oct 20, 1998 | Issued |
Array
(
[id] => 6921606
[patent_doc_number] => 20010029091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-11
[patent_title] => 'METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE COMPRISING AN ORGANIC- CONTAINING MATERIAL'
[patent_app_type] => new
[patent_app_number] => 09/175247
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2921
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20010029091.pdf
[firstpage_image] =>[orig_patent_app_number] => 09175247
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175247 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE COMPRISING AN ORGANIC- CONTAINING MATERIAL | Oct 19, 1998 | Abandoned |
Array
(
[id] => 4169632
[patent_doc_number] => 06140223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition'
[patent_app_type] => 1
[patent_app_number] => 9/175698
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2398
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140223.pdf
[firstpage_image] =>[orig_patent_app_number] => 175698
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175698 | Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition | Oct 19, 1998 | Issued |
Array
(
[id] => 1080531
[patent_doc_number] => 06835672
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-28
[patent_title] => 'Selective oxidation for semiconductor device fabrication'
[patent_app_type] => B1
[patent_app_number] => 09/173129
[patent_app_country] => US
[patent_app_date] => 1998-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3147
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835672.pdf
[firstpage_image] =>[orig_patent_app_number] => 09173129
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/173129 | Selective oxidation for semiconductor device fabrication | Oct 14, 1998 | Issued |
Array
(
[id] => 4156095
[patent_doc_number] => 06156634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method of fabricating local interconnect'
[patent_app_type] => 1
[patent_app_number] => 9/173508
[patent_app_country] => US
[patent_app_date] => 1998-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2478
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156634.pdf
[firstpage_image] =>[orig_patent_app_number] => 173508
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/173508 | Method of fabricating local interconnect | Oct 14, 1998 | Issued |
Array
(
[id] => 4320074
[patent_doc_number] => 06242808
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Semiconductor device with copper wiring and semiconductor device manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/167540
[patent_app_country] => US
[patent_app_date] => 1998-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 4246
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242808.pdf
[firstpage_image] =>[orig_patent_app_number] => 167540
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167540 | Semiconductor device with copper wiring and semiconductor device manufacturing method | Oct 6, 1998 | Issued |
Array
(
[id] => 4359137
[patent_doc_number] => 06255231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Method for forming a gate oxide layer'
[patent_app_type] => 1
[patent_app_number] => 9/165398
[patent_app_country] => US
[patent_app_date] => 1998-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 5600
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/255/06255231.pdf
[firstpage_image] =>[orig_patent_app_number] => 165398
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/165398 | Method for forming a gate oxide layer | Oct 1, 1998 | Issued |
Array
(
[id] => 4327377
[patent_doc_number] => 06319822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Process for forming an integrated contact or via'
[patent_app_type] => 1
[patent_app_number] => 9/164999
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4390
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319822.pdf
[firstpage_image] =>[orig_patent_app_number] => 164999
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164999 | Process for forming an integrated contact or via | Sep 30, 1998 | Issued |
Array
(
[id] => 5798491
[patent_doc_number] => 20020008257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-24
[patent_title] => 'MOSFET GATE ELECTRODES HAVING PERFORMANCE TUNED WORK FUNCTIONS AND METHODS OF MAKING SAME'
[patent_app_type] => new
[patent_app_number] => 09/165009
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3260
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20020008257.pdf
[firstpage_image] =>[orig_patent_app_number] => 09165009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/165009 | MOSFET GATE ELECTRODES HAVING PERFORMANCE TUNED WORK FUNCTIONS AND METHODS OF MAKING SAME | Sep 29, 1998 | Abandoned |
Array
(
[id] => 1314416
[patent_doc_number] => 06614097
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/164069
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2383
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/614/06614097.pdf
[firstpage_image] =>[orig_patent_app_number] => 09164069
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164069 | Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device | Sep 29, 1998 | Issued |
Array
(
[id] => 4408092
[patent_doc_number] => 06265256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'MOS transistor with minimal overlap between gate and source/drain extensions'
[patent_app_type] => 1
[patent_app_number] => 9/156238
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 2699
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/265/06265256.pdf
[firstpage_image] =>[orig_patent_app_number] => 156238
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156238 | MOS transistor with minimal overlap between gate and source/drain extensions | Sep 16, 1998 | Issued |
Array
(
[id] => 4207009
[patent_doc_number] => 06027999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Pad definition to achieve highly reflective plate without affecting bondability'
[patent_app_type] => 1
[patent_app_number] => 9/151159
[patent_app_country] => US
[patent_app_date] => 1998-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1739
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/027/06027999.pdf
[firstpage_image] =>[orig_patent_app_number] => 151159
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151159 | Pad definition to achieve highly reflective plate without affecting bondability | Sep 9, 1998 | Issued |
Array
(
[id] => 1500427
[patent_doc_number] => 06486060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'Low resistance semiconductor process and structures'
[patent_app_type] => B2
[patent_app_number] => 09/146639
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2409
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486060.pdf
[firstpage_image] =>[orig_patent_app_number] => 09146639
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146639 | Low resistance semiconductor process and structures | Sep 2, 1998 | Issued |
Array
(
[id] => 1394790
[patent_doc_number] => 06541375
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'DC sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention'
[patent_app_type] => B1
[patent_app_number] => 09/128249
[patent_app_country] => US
[patent_app_date] => 1998-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 52
[patent_no_of_words] => 19148
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/541/06541375.pdf
[firstpage_image] =>[orig_patent_app_number] => 09128249
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/128249 | DC sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention | Aug 2, 1998 | Issued |
Array
(
[id] => 4301339
[patent_doc_number] => 06198142
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Transistor with minimal junction capacitance and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/127349
[patent_app_country] => US
[patent_app_date] => 1998-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 9849
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/198/06198142.pdf
[firstpage_image] =>[orig_patent_app_number] => 127349
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/127349 | Transistor with minimal junction capacitance and method of fabrication | Jul 30, 1998 | Issued |
Array
(
[id] => 4084072
[patent_doc_number] => 06162698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Method of manufacturing a capacitor in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/105278
[patent_app_country] => US
[patent_app_date] => 1998-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 2024
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/162/06162698.pdf
[firstpage_image] =>[orig_patent_app_number] => 105278
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105278 | Method of manufacturing a capacitor in a semiconductor device | Jun 25, 1998 | Issued |
Array
(
[id] => 4136779
[patent_doc_number] => 06015753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Method of forming a self-aligned silicide'
[patent_app_type] => 1
[patent_app_number] => 9/103888
[patent_app_country] => US
[patent_app_date] => 1998-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2800
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/015/06015753.pdf
[firstpage_image] =>[orig_patent_app_number] => 103888
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/103888 | Method of forming a self-aligned silicide | Jun 23, 1998 | Issued |
| 09/099978 | SI/SIGE OPTOELECTRONIC INTEGRATED CIRCUITS | Jun 18, 1998 | Abandoned |
Array
(
[id] => 4169267
[patent_doc_number] => 06140199
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method and arrangement of a buried capacitor, and a buried capacitor arranged according to said method'
[patent_app_type] => 1
[patent_app_number] => 9/090218
[patent_app_country] => US
[patent_app_date] => 1998-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 1764
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140199.pdf
[firstpage_image] =>[orig_patent_app_number] => 090218
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/090218 | Method and arrangement of a buried capacitor, and a buried capacitor arranged according to said method | Jun 3, 1998 | Issued |