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Ginette Peralta

Examiner (ID: 17098)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1494285 [patent_doc_number] => 06342434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Methods of processing semiconductor wafer, and producing IC card, and carrier' [patent_app_type] => B1 [patent_app_number] => 09/077548 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 61 [patent_no_of_words] => 12447 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342434.pdf [firstpage_image] =>[orig_patent_app_number] => 09077548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/077548
Methods of processing semiconductor wafer, and producing IC card, and carrier May 31, 1998 Issued
Array ( [id] => 4294487 [patent_doc_number] => 06197702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Fabrication process of a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/086568 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 10848 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197702.pdf [firstpage_image] =>[orig_patent_app_number] => 086568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086568
Fabrication process of a semiconductor integrated circuit device May 28, 1998 Issued
Array ( [id] => 1603248 [patent_doc_number] => 06433428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same' [patent_app_type] => B1 [patent_app_number] => 09/086958 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 8499 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433428.pdf [firstpage_image] =>[orig_patent_app_number] => 09086958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086958
Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same May 28, 1998 Issued
Array ( [id] => 1212906 [patent_doc_number] => 06709991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method of fabricating semiconductor device with capacitor' [patent_app_type] => B1 [patent_app_number] => 09/084578 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 7774 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709991.pdf [firstpage_image] =>[orig_patent_app_number] => 09084578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084578
Method of fabricating semiconductor device with capacitor May 25, 1998 Issued
Array ( [id] => 3993879 [patent_doc_number] => 05985729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method for manufacturing a capacitor of a trench DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/054128 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985729.pdf [firstpage_image] =>[orig_patent_app_number] => 054128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054128
Method for manufacturing a capacitor of a trench DRAM cell Apr 1, 1998 Issued
Array ( [id] => 1041009 [patent_doc_number] => 06870263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Device interconnection' [patent_app_type] => utility [patent_app_number] => 09/052688 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4221 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870263.pdf [firstpage_image] =>[orig_patent_app_number] => 09052688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052688
Device interconnection Mar 30, 1998 Issued
Array ( [id] => 4185745 [patent_doc_number] => 06093614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Memory cell structure and fabrication' [patent_app_type] => 1 [patent_app_number] => 9/034519 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5100 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093614.pdf [firstpage_image] =>[orig_patent_app_number] => 034519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034519
Memory cell structure and fabrication Mar 3, 1998 Issued
Array ( [id] => 4191803 [patent_doc_number] => 06130165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 8/997499 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2553 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130165.pdf [firstpage_image] =>[orig_patent_app_number] => 997499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997499
Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates Dec 22, 1997 Issued
Array ( [id] => 4117154 [patent_doc_number] => 06071810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of filling contact holes and wiring grooves of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/997328 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 218 [patent_no_of_words] => 66437 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071810.pdf [firstpage_image] =>[orig_patent_app_number] => 997328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997328
Method of filling contact holes and wiring grooves of a semiconductor device Dec 22, 1997 Issued
Array ( [id] => 4245709 [patent_doc_number] => 06136645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Fabrication method for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/979112 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 4770 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136645.pdf [firstpage_image] =>[orig_patent_app_number] => 979112 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979112
Fabrication method for semiconductor memory device Nov 25, 1997 Issued
Array ( [id] => 4344482 [patent_doc_number] => 06284633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/976469 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2253 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284633.pdf [firstpage_image] =>[orig_patent_app_number] => 976469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976469
Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode Nov 23, 1997 Issued
Array ( [id] => 4206227 [patent_doc_number] => 06086642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Fabrication method of solid electrolytic capacitor' [patent_app_type] => 1 [patent_app_number] => 8/974887 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4295 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/086/06086642.pdf [firstpage_image] =>[orig_patent_app_number] => 974887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974887
Fabrication method of solid electrolytic capacitor Nov 19, 1997 Issued
Array ( [id] => 1578151 [patent_doc_number] => 06448145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'Capacitor for semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 08/965486 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3537 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448145.pdf [firstpage_image] =>[orig_patent_app_number] => 08965486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965486
Capacitor for semiconductor device and method for manufacturing the same Nov 5, 1997 Issued
Array ( [id] => 4003360 [patent_doc_number] => 06004886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Liquid phase deposition method for forming silicon dioxide film on HGCDTE or other II-VI semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/960913 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4431 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004886.pdf [firstpage_image] =>[orig_patent_app_number] => 960913 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960913
Liquid phase deposition method for forming silicon dioxide film on HGCDTE or other II-VI semiconductor substrate Oct 29, 1997 Issued
Array ( [id] => 4329470 [patent_doc_number] => 06313027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method for low thermal budget metal filling and planarization of contacts vias and trenches' [patent_app_type] => 1 [patent_app_number] => 8/944140 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8819 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313027.pdf [firstpage_image] =>[orig_patent_app_number] => 944140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944140
Method for low thermal budget metal filling and planarization of contacts vias and trenches Oct 5, 1997 Issued
Array ( [id] => 4145900 [patent_doc_number] => 06063688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition' [patent_app_type] => 1 [patent_app_number] => 8/939578 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 40 [patent_no_of_words] => 6160 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063688.pdf [firstpage_image] =>[orig_patent_app_number] => 939578 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939578
Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition Sep 28, 1997 Issued
Array ( [id] => 4102744 [patent_doc_number] => 06051491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Multilevel interconnection structure for integrated circuits and method of producing same' [patent_app_type] => 1 [patent_app_number] => 8/938634 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2488 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051491.pdf [firstpage_image] =>[orig_patent_app_number] => 938634 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938634
Multilevel interconnection structure for integrated circuits and method of producing same Sep 25, 1997 Issued
Array ( [id] => 4084455 [patent_doc_number] => 06162725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Process of patterning conductive layer into electrode through lift-off using photo-resist mask imperfectly covered with the conductive layer' [patent_app_type] => 1 [patent_app_number] => 8/933077 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 3925 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162725.pdf [firstpage_image] =>[orig_patent_app_number] => 933077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933077
Process of patterning conductive layer into electrode through lift-off using photo-resist mask imperfectly covered with the conductive layer Sep 17, 1997 Issued
Array ( [id] => 4267013 [patent_doc_number] => 06306727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Advanced isolation process for large memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/912505 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3998 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306727.pdf [firstpage_image] =>[orig_patent_app_number] => 912505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912505
Advanced isolation process for large memory arrays Aug 17, 1997 Issued
Array ( [id] => 4267577 [patent_doc_number] => 06306763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Enhanced salicidation technique' [patent_app_type] => 1 [patent_app_number] => 8/896397 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6098 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306763.pdf [firstpage_image] =>[orig_patent_app_number] => 896397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896397
Enhanced salicidation technique Jul 17, 1997 Issued
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