
Ginette Peralta
Examiner (ID: 17098)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1494285
[patent_doc_number] => 06342434
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-29
[patent_title] => 'Methods of processing semiconductor wafer, and producing IC card, and carrier'
[patent_app_type] => B1
[patent_app_number] => 09/077548
[patent_app_country] => US
[patent_app_date] => 1998-06-01
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 61
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[pdf_file] => patents/06/342/06342434.pdf
[firstpage_image] =>[orig_patent_app_number] => 09077548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/077548 | Methods of processing semiconductor wafer, and producing IC card, and carrier | May 31, 1998 | Issued |
Array
(
[id] => 4294487
[patent_doc_number] => 06197702
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[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Fabrication process of a semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 9/086568
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[patent_app_date] => 1998-05-29
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[firstpage_image] =>[orig_patent_app_number] => 086568
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Array
(
[id] => 1603248
[patent_doc_number] => 06433428
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same'
[patent_app_type] => B1
[patent_app_number] => 09/086958
[patent_app_country] => US
[patent_app_date] => 1998-05-29
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[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/06/433/06433428.pdf
[firstpage_image] =>[orig_patent_app_number] => 09086958
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086958 | Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same | May 28, 1998 | Issued |
Array
(
[id] => 1212906
[patent_doc_number] => 06709991
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Method of fabricating semiconductor device with capacitor'
[patent_app_type] => B1
[patent_app_number] => 09/084578
[patent_app_country] => US
[patent_app_date] => 1998-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[firstpage_image] =>[orig_patent_app_number] => 09084578
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/084578 | Method of fabricating semiconductor device with capacitor | May 25, 1998 | Issued |
Array
(
[id] => 3993879
[patent_doc_number] => 05985729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for manufacturing a capacitor of a trench DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 9/054128
[patent_app_country] => US
[patent_app_date] => 1998-04-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/985/05985729.pdf
[firstpage_image] =>[orig_patent_app_number] => 054128
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/054128 | Method for manufacturing a capacitor of a trench DRAM cell | Apr 1, 1998 | Issued |
Array
(
[id] => 1041009
[patent_doc_number] => 06870263
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Device interconnection'
[patent_app_type] => utility
[patent_app_number] => 09/052688
[patent_app_country] => US
[patent_app_date] => 1998-03-31
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[pdf_file] => patents/06/870/06870263.pdf
[firstpage_image] =>[orig_patent_app_number] => 09052688
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052688 | Device interconnection | Mar 30, 1998 | Issued |
Array
(
[id] => 4185745
[patent_doc_number] => 06093614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Memory cell structure and fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/034519
[patent_app_country] => US
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[pdf_file] => patents/06/093/06093614.pdf
[firstpage_image] =>[orig_patent_app_number] => 034519
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/034519 | Memory cell structure and fabrication | Mar 3, 1998 | Issued |
Array
(
[id] => 4191803
[patent_doc_number] => 06130165
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates'
[patent_app_type] => 1
[patent_app_number] => 8/997499
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/130/06130165.pdf
[firstpage_image] =>[orig_patent_app_number] => 997499
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997499 | Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates | Dec 22, 1997 | Issued |
Array
(
[id] => 4117154
[patent_doc_number] => 06071810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method of filling contact holes and wiring grooves of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/997328
[patent_app_country] => US
[patent_app_date] => 1997-12-23
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[pdf_file] => patents/06/071/06071810.pdf
[firstpage_image] =>[orig_patent_app_number] => 997328
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997328 | Method of filling contact holes and wiring grooves of a semiconductor device | Dec 22, 1997 | Issued |
Array
(
[id] => 4245709
[patent_doc_number] => 06136645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Fabrication method for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/979112
[patent_app_country] => US
[patent_app_date] => 1997-11-26
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[pdf_file] => patents/06/136/06136645.pdf
[firstpage_image] =>[orig_patent_app_number] => 979112
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979112 | Fabrication method for semiconductor memory device | Nov 25, 1997 | Issued |
Array
(
[id] => 4344482
[patent_doc_number] => 06284633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/976469
[patent_app_country] => US
[patent_app_date] => 1997-11-24
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[pdf_file] => patents/06/284/06284633.pdf
[firstpage_image] =>[orig_patent_app_number] => 976469
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/976469 | Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode | Nov 23, 1997 | Issued |
Array
(
[id] => 4206227
[patent_doc_number] => 06086642
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Fabrication method of solid electrolytic capacitor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/974887 | Fabrication method of solid electrolytic capacitor | Nov 19, 1997 | Issued |
Array
(
[id] => 1578151
[patent_doc_number] => 06448145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-10
[patent_title] => 'Capacitor for semiconductor device and method for manufacturing the same'
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[firstpage_image] =>[orig_patent_app_number] => 08965486
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Array
(
[id] => 4003360
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[patent_title] => 'Liquid phase deposition method for forming silicon dioxide film on HGCDTE or other II-VI semiconductor substrate'
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Array
(
[id] => 4329470
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[patent_title] => 'Method for low thermal budget metal filling and planarization of contacts vias and trenches'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/944140 | Method for low thermal budget metal filling and planarization of contacts vias and trenches | Oct 5, 1997 | Issued |
Array
(
[id] => 4145900
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[patent_title] => 'Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition'
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Array
(
[id] => 4102744
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[patent_title] => 'Multilevel interconnection structure for integrated circuits and method of producing same'
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Array
(
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Array
(
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[patent_title] => 'Advanced isolation process for large memory arrays'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912505 | Advanced isolation process for large memory arrays | Aug 17, 1997 | Issued |
Array
(
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[patent_title] => 'Enhanced salicidation technique'
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[firstpage_image] =>[orig_patent_app_number] => 896397
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896397 | Enhanced salicidation technique | Jul 17, 1997 | Issued |