Search

Ginette Peralta

Examiner (ID: 17098)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6807330 [patent_doc_number] => 20030197269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Test fixture for semiconductor packages' [patent_app_type] => new [patent_app_number] => 10/192378 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3173 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197269.pdf [firstpage_image] =>[orig_patent_app_number] => 10192378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192378
Test fixture for semiconductor packages Jul 9, 2002 Abandoned
Array ( [id] => 6787795 [patent_doc_number] => 20030139034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Dual damascene structure and method of making same' [patent_app_type] => new [patent_app_number] => 10/064364 [patent_app_country] => US [patent_app_date] => 2002-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2472 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139034.pdf [firstpage_image] =>[orig_patent_app_number] => 10064364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064364
Dual damascene structure and method of making same Jul 6, 2002 Abandoned
Array ( [id] => 6044326 [patent_doc_number] => 20020167040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Capacitor for semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/186673 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3608 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167040.pdf [firstpage_image] =>[orig_patent_app_number] => 10186673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186673
Capacitor for semiconductor device and method for manufacturing the same Jul 1, 2002 Issued
Array ( [id] => 1149285 [patent_doc_number] => 06770523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method for semiconductor wafer planarization by CMP stop layer formation' [patent_app_type] => B1 [patent_app_number] => 10/190397 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770523.pdf [firstpage_image] =>[orig_patent_app_number] => 10190397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190397
Method for semiconductor wafer planarization by CMP stop layer formation Jul 1, 2002 Issued
Array ( [id] => 1386794 [patent_doc_number] => 06555888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Electrostatic discharge protection for sensors' [patent_app_type] => B2 [patent_app_number] => 10/186801 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555888.pdf [firstpage_image] =>[orig_patent_app_number] => 10186801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186801
Electrostatic discharge protection for sensors Jun 30, 2002 Issued
Array ( [id] => 978483 [patent_doc_number] => 06929713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'In-situ photoresist removal by an attachable chamber with light source' [patent_app_type] => utility [patent_app_number] => 10/186533 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3013 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/929/06929713.pdf [firstpage_image] =>[orig_patent_app_number] => 10186533 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186533
In-situ photoresist removal by an attachable chamber with light source Jun 30, 2002 Issued
Array ( [id] => 1245760 [patent_doc_number] => 06677240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for patterning dense and isolated features on semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 10/186033 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677240.pdf [firstpage_image] =>[orig_patent_app_number] => 10186033 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186033
Method for patterning dense and isolated features on semiconductor devices Jun 27, 2002 Issued
Array ( [id] => 1031077 [patent_doc_number] => 06878629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Method for detecting CMP endpoint in acidic slurries' [patent_app_type] => utility [patent_app_number] => 10/185818 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3892 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878629.pdf [firstpage_image] =>[orig_patent_app_number] => 10185818 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185818
Method for detecting CMP endpoint in acidic slurries Jun 26, 2002 Issued
Array ( [id] => 6651334 [patent_doc_number] => 20030008486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method of fabricating a MOS transistor with a drain extension and corresponding transistor' [patent_app_type] => new [patent_app_number] => 10/184036 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2779 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008486.pdf [firstpage_image] =>[orig_patent_app_number] => 10184036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184036
Method of fabricating a MOS transistor with a drain extension and corresponding transistor Jun 26, 2002 Issued
Array ( [id] => 982319 [patent_doc_number] => 06927163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and apparatus for manufacturing a barrier layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/180754 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2162 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927163.pdf [firstpage_image] =>[orig_patent_app_number] => 10180754 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180754
Method and apparatus for manufacturing a barrier layer of semiconductor device Jun 25, 2002 Issued
Array ( [id] => 6327408 [patent_doc_number] => 20020197830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method and apparatus for producing group III nitride compound semiconductor' [patent_app_type] => new [patent_app_number] => 10/178853 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6562 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197830.pdf [firstpage_image] =>[orig_patent_app_number] => 10178853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178853
Method and apparatus for producing group III nitride compound semiconductor Jun 24, 2002 Issued
Array ( [id] => 975486 [patent_doc_number] => 06933221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method for underfilling semiconductor components using no flow underfill' [patent_app_type] => utility [patent_app_number] => 10/178703 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 5449 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933221.pdf [firstpage_image] =>[orig_patent_app_number] => 10178703 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178703
Method for underfilling semiconductor components using no flow underfill Jun 23, 2002 Issued
Array ( [id] => 6048256 [patent_doc_number] => 20020168872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Insulators for high density circuits' [patent_app_type] => new [patent_app_number] => 10/179151 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3651 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20020168872.pdf [firstpage_image] =>[orig_patent_app_number] => 10179151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179151
Insulators for high density circuits Jun 23, 2002 Issued
Array ( [id] => 999536 [patent_doc_number] => 06911386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Integrated process for fuse opening and passivation process for CU/LOW-K IMD' [patent_app_type] => utility [patent_app_number] => 10/176943 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6632 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911386.pdf [firstpage_image] =>[orig_patent_app_number] => 10176943 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176943
Integrated process for fuse opening and passivation process for CU/LOW-K IMD Jun 20, 2002 Issued
Array ( [id] => 1097533 [patent_doc_number] => 06822339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/167573 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 11396 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822339.pdf [firstpage_image] =>[orig_patent_app_number] => 10167573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167573
Semiconductor device Jun 12, 2002 Issued
Array ( [id] => 6701734 [patent_doc_number] => 20030224614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Chamber having a protective layer' [patent_app_type] => new [patent_app_number] => 10/159363 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6692 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224614.pdf [firstpage_image] =>[orig_patent_app_number] => 10159363 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159363
Chamber having a protective layer May 30, 2002 Issued
Array ( [id] => 1056804 [patent_doc_number] => 06855969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Semiconductor device having a plurality of gate electrodes and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/155998 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 36 [patent_no_of_words] => 5037 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855969.pdf [firstpage_image] =>[orig_patent_app_number] => 10155998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155998
Semiconductor device having a plurality of gate electrodes and manufacturing method thereof May 28, 2002 Issued
Array ( [id] => 1027959 [patent_doc_number] => 06881675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method and system for reducing wafer edge tungsten residue utilizing a spin etch' [patent_app_type] => utility [patent_app_number] => 10/146864 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2583 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/881/06881675.pdf [firstpage_image] =>[orig_patent_app_number] => 10146864 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146864
Method and system for reducing wafer edge tungsten residue utilizing a spin etch May 14, 2002 Issued
Array ( [id] => 6636443 [patent_doc_number] => 20030211720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Method of wafer level chip scale packaging' [patent_app_type] => new [patent_app_number] => 10/144074 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6890 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211720.pdf [firstpage_image] =>[orig_patent_app_number] => 10144074 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144074
Method of wafer level chip scale packaging May 12, 2002 Issued
Array ( [id] => 6176670 [patent_doc_number] => 20020155656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Manufacturing method of semiconductor integrated circuit device, and semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/142063 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 69 [patent_no_of_words] => 24287 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155656.pdf [firstpage_image] =>[orig_patent_app_number] => 10142063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142063
Manufacturing method of semiconductor integrated circuit device, and semiconductor integrated circuit device May 9, 2002 Issued
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