
Ginette Peralta
Examiner (ID: 17098)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1239653
[patent_doc_number] => 06686260
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Process for producing thermally annealed wafers having improved internal gettering'
[patent_app_type] => B2
[patent_app_number] => 10/067070
[patent_app_country] => US
[patent_app_date] => 2002-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 10507
[patent_no_of_claims] => 30
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[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686260.pdf
[firstpage_image] =>[orig_patent_app_number] => 10067070
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/067070 | Process for producing thermally annealed wafers having improved internal gettering | Feb 3, 2002 | Issued |
Array
(
[id] => 993956
[patent_doc_number] => 06917056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-12
[patent_title] => 'Optoelectronic submount having an on-edge optoelectronic device'
[patent_app_type] => utility
[patent_app_number] => 10/066299
[patent_app_country] => US
[patent_app_date] => 2002-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/917/06917056.pdf
[firstpage_image] =>[orig_patent_app_number] => 10066299
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/066299 | Optoelectronic submount having an on-edge optoelectronic device | Jan 30, 2002 | Issued |
Array
(
[id] => 5933372
[patent_doc_number] => 20020060331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-23
[patent_title] => 'Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor'
[patent_app_type] => new
[patent_app_number] => 10/053543
[patent_app_country] => US
[patent_app_date] => 2002-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 9530
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20020060331.pdf
[firstpage_image] =>[orig_patent_app_number] => 10053543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/053543 | Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor | Jan 23, 2002 | Issued |
| 09/683579 | Dual damascene structure and method of making same | Jan 21, 2002 | Abandoned |
Array
(
[id] => 6683441
[patent_doc_number] => 20030119305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Mask layer and dual damascene interconnect structure in a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/026257
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 4479
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[pdf_file] => publications/A1/0119/20030119305.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026257 | Mask layer and dual damascene interconnect structure in a semiconductor device | Dec 20, 2001 | Abandoned |
Array
(
[id] => 6668986
[patent_doc_number] => 20030113970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Implanted asymmetric doped polysilicon gate FinFET'
[patent_app_type] => new
[patent_app_number] => 09/683328
[patent_app_country] => US
[patent_app_date] => 2001-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3070
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20030113970.pdf
[firstpage_image] =>[orig_patent_app_number] => 09683328
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/683328 | Implanted asymmetric doped polysilicon gate FinFET | Dec 13, 2001 | Issued |
Array
(
[id] => 1409828
[patent_doc_number] => 06528403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-04
[patent_title] => 'Fabrication process of a semiconductor integrated circuit device'
[patent_app_type] => B2
[patent_app_number] => 10/013454
[patent_app_country] => US
[patent_app_date] => 2001-12-13
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 10918
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/528/06528403.pdf
[firstpage_image] =>[orig_patent_app_number] => 10013454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/013454 | Fabrication process of a semiconductor integrated circuit device | Dec 12, 2001 | Issued |
Array
(
[id] => 6696936
[patent_doc_number] => 20030109130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Dual-gate process with CMP'
[patent_app_type] => new
[patent_app_number] => 10/010258
[patent_app_country] => US
[patent_app_date] => 2001-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1050
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20030109130.pdf
[firstpage_image] =>[orig_patent_app_number] => 10010258
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/010258 | Dual-gate process with CMP | Dec 6, 2001 | Abandoned |
Array
(
[id] => 6242479
[patent_doc_number] => 20020045322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-18
[patent_title] => 'Method of depositing tungsten nitride using a source gas comprising silicon'
[patent_app_type] => new
[patent_app_number] => 10/004714
[patent_app_country] => US
[patent_app_date] => 2001-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1655
[patent_no_of_claims] => 74
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[pdf_file] => publications/A1/0045/20020045322.pdf
[firstpage_image] =>[orig_patent_app_number] => 10004714
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/004714 | Method of depositing tungsten nitride using a source gas comprising silicon | Dec 4, 2001 | Issued |
Array
(
[id] => 1140851
[patent_doc_number] => 06781184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Barrier layers for protecting metal oxides from hydrogen degradation'
[patent_app_type] => B2
[patent_app_number] => 09/998469
[patent_app_country] => US
[patent_app_date] => 2001-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/781/06781184.pdf
[firstpage_image] =>[orig_patent_app_number] => 09998469
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998469 | Barrier layers for protecting metal oxides from hydrogen degradation | Nov 28, 2001 | Issued |
Array
(
[id] => 6861249
[patent_doc_number] => 20030092257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-15
[patent_title] => 'Method for fabricating metal interconnects'
[patent_app_type] => new
[patent_app_number] => 09/997353
[patent_app_country] => US
[patent_app_date] => 2001-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1539
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[pdf_file] => publications/A1/0092/20030092257.pdf
[firstpage_image] =>[orig_patent_app_number] => 09997353
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/997353 | Method for fabricating metal interconnects | Nov 26, 2001 | Abandoned |
Array
(
[id] => 1339955
[patent_doc_number] => 06589855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-08
[patent_title] => 'Methods of processing semiconductor wafer and producing IC card, and carrier'
[patent_app_type] => B2
[patent_app_number] => 09/991750
[patent_app_country] => US
[patent_app_date] => 2001-11-26
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[pdf_file] => patents/06/589/06589855.pdf
[firstpage_image] =>[orig_patent_app_number] => 09991750
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/991750 | Methods of processing semiconductor wafer and producing IC card, and carrier | Nov 25, 2001 | Issued |
Array
(
[id] => 1358723
[patent_doc_number] => 06573158
[patent_country] => US
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[patent_issue_date] => 2003-06-03
[patent_title] => 'Methods of processing semiconductor wafer and producing IC card, and carrier'
[patent_app_type] => B2
[patent_app_number] => 09/991747
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/991747 | Methods of processing semiconductor wafer and producing IC card, and carrier | Nov 25, 2001 | Issued |
Array
(
[id] => 6801331
[patent_doc_number] => 20030096496
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[patent_issue_date] => 2003-05-22
[patent_title] => 'Method of forming dual damascene structure'
[patent_app_type] => new
[patent_app_number] => 09/990163
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09990163
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/990163 | Method of forming dual damascene structure | Nov 19, 2001 | Abandoned |
Array
(
[id] => 1175372
[patent_doc_number] => 06746950
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[patent_kind] => B2
[patent_issue_date] => 2004-06-08
[patent_title] => 'Low temperature aluminum planarization process'
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[patent_app_number] => 09/992743
[patent_app_country] => US
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[pdf_file] => patents/06/746/06746950.pdf
[firstpage_image] =>[orig_patent_app_number] => 09992743
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/992743 | Low temperature aluminum planarization process | Nov 13, 2001 | Issued |
Array
(
[id] => 5922033
[patent_doc_number] => 20020115269
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[patent_issue_date] => 2002-08-22
[patent_title] => 'Method of depositing amorphous silicon based films having controlled conductivity'
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[firstpage_image] =>[orig_patent_app_number] => 10052878
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052878 | Method of depositing amorphous silicon based films having controlled conductivity | Nov 1, 2001 | Abandoned |
Array
(
[id] => 6792170
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[patent_issue_date] => 2003-05-08
[patent_title] => 'Hard mask damascene process used to form a semiconductor device'
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[patent_app_number] => 10/007929
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[pdf_file] => publications/A1/0087/20030087514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10007929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/007929 | Hard mask damascene process used to form a semiconductor device | Nov 1, 2001 | Abandoned |
Array
(
[id] => 783488
[patent_doc_number] => 06992391
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'Dual-damascene interconnects without an etch stop layer by alternating ILDs'
[patent_app_type] => utility
[patent_app_number] => 09/968459
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/968459 | Dual-damascene interconnects without an etch stop layer by alternating ILDs | Sep 27, 2001 | Issued |
Array
(
[id] => 1281467
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[patent_title] => 'Method for forming Co-W-P-Au films'
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[patent_app_number] => 09/966629
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[firstpage_image] =>[orig_patent_app_number] => 09966629
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966629 | Method for forming Co-W-P-Au films | Sep 26, 2001 | Issued |
Array
(
[id] => 1155882
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[patent_issue_date] => 2004-07-20
[patent_title] => 'Method for forming metal wire interconnection in semiconductor devices using dual damascene process'
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[patent_app_number] => 09/934499
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[firstpage_image] =>[orig_patent_app_number] => 09934499
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/934499 | Method for forming metal wire interconnection in semiconductor devices using dual damascene process | Aug 21, 2001 | Issued |