
Ginette Peralta
Examiner (ID: 17496)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5998062
[patent_doc_number] => 20020027621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Array substrate for a liquid crystal display device and method for fabricating thereof'
[patent_app_type] => new
[patent_app_number] => 09/893962
[patent_app_country] => US
[patent_app_date] => 2001-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6049
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20020027621.pdf
[firstpage_image] =>[orig_patent_app_number] => 09893962
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/893962 | Array substrate for a liquid crystal display and method for fabricating thereof | Jun 28, 2001 | Issued |
Array
(
[id] => 7064909
[patent_doc_number] => 20010044164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-22
[patent_title] => 'Capacitor containing amorphous and polycrystalline ferroelectric films and fabrication method therefor, and method for forming amorphous ferroelectric film'
[patent_app_type] => new
[patent_app_number] => 09/884029
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0044/20010044164.pdf
[firstpage_image] =>[orig_patent_app_number] => 09884029
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/884029 | Capacitor containing amorphous and polycrystalline ferroelectric films and fabrication method therefor, and method for forming amorphous ferroelectric film | Jun 19, 2001 | Issued |
Array
(
[id] => 6651392
[patent_doc_number] => 20030008496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Method for making an electronic component with self-aligned drain and gate, in damascene architecture'
[patent_app_type] => new
[patent_app_number] => 10/030175
[patent_app_country] => US
[patent_app_date] => 2002-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0008/20030008496.pdf
[firstpage_image] =>[orig_patent_app_number] => 10030175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/030175 | Method for making an electronic component with self-aligned drain and gate, in damascene architecture | Jun 7, 2001 | Issued |
Array
(
[id] => 1318498
[patent_doc_number] => 06605533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-12
[patent_title] => 'Process for forming low resistance metal silicide local interconnects'
[patent_app_type] => B2
[patent_app_number] => 09/877280
[patent_app_country] => US
[patent_app_date] => 2001-06-08
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 5711
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/605/06605533.pdf
[firstpage_image] =>[orig_patent_app_number] => 09877280
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/877280 | Process for forming low resistance metal silicide local interconnects | Jun 7, 2001 | Issued |
| 09/856466 | Liquid-crystal display device | Jun 6, 2001 | Abandoned |
Array
(
[id] => 1440092
[patent_doc_number] => 06495443
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Method of re-working copper damascene wafers'
[patent_app_type] => B1
[patent_app_number] => 09/874513
[patent_app_country] => US
[patent_app_date] => 2001-06-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/495/06495443.pdf
[firstpage_image] =>[orig_patent_app_number] => 09874513
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/874513 | Method of re-working copper damascene wafers | Jun 4, 2001 | Issued |
Array
(
[id] => 1402389
[patent_doc_number] => 06534407
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[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method for reducing dishing effects during a chemical mechanical polishing process'
[patent_app_type] => B2
[patent_app_number] => 09/871663
[patent_app_country] => US
[patent_app_date] => 2001-06-04
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[pdf_file] => patents/06/534/06534407.pdf
[firstpage_image] =>[orig_patent_app_number] => 09871663
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871663 | Method for reducing dishing effects during a chemical mechanical polishing process | Jun 3, 2001 | Issued |
Array
(
[id] => 1440161
[patent_doc_number] => 06495477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-17
[patent_title] => 'Method for forming a nitridized interface on a semiconductor substrate'
[patent_app_type] => B2
[patent_app_number] => 09/862348
[patent_app_country] => US
[patent_app_date] => 2001-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 6549
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[pdf_file] => patents/06/495/06495477.pdf
[firstpage_image] =>[orig_patent_app_number] => 09862348
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/862348 | Method for forming a nitridized interface on a semiconductor substrate | May 20, 2001 | Issued |
Array
(
[id] => 6946957
[patent_doc_number] => 20010020710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-13
[patent_title] => 'Semiconductor memory device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 09/816399
[patent_app_country] => US
[patent_app_date] => 2001-03-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0020/20010020710.pdf
[firstpage_image] =>[orig_patent_app_number] => 09816399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/816399 | Semiconductor memory device and manufacturing method thereof | Mar 25, 2001 | Issued |
Array
(
[id] => 6892082
[patent_doc_number] => 20010018244
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[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Capacitor for semiconductor device and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/802910
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[pdf_file] => publications/A1/0018/20010018244.pdf
[firstpage_image] =>[orig_patent_app_number] => 09802910
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802910 | Capacitor for semiconductor device and method for manufacturing the same | Mar 11, 2001 | Issued |
Array
(
[id] => 1216469
[patent_doc_number] => 06706608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-16
[patent_title] => 'Memory cell capacitors having an over/under configuration'
[patent_app_type] => B2
[patent_app_number] => 09/795548
[patent_app_country] => US
[patent_app_date] => 2001-02-28
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[pdf_file] => patents/06/706/06706608.pdf
[firstpage_image] =>[orig_patent_app_number] => 09795548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795548 | Memory cell capacitors having an over/under configuration | Feb 27, 2001 | Issued |
Array
(
[id] => 6889415
[patent_doc_number] => 20010024870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-27
[patent_title] => 'Fabrication process of a semiconductor integrated circuit device'
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[patent_app_number] => 09/773000
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[pdf_file] => publications/A1/0024/20010024870.pdf
[firstpage_image] =>[orig_patent_app_number] => 09773000
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/773000 | Fabrication process of a semiconductor integrated circuit device | Jan 30, 2001 | Issued |
Array
(
[id] => 6890560
[patent_doc_number] => 20010007791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-12
[patent_title] => 'Method of reducing stress corrosion induced voiding of patterned metal layers'
[patent_app_type] => new-utility
[patent_app_number] => 09/765426
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/765426 | Method of reducing stress corrosion induced voiding of patterned metal layers | Jan 21, 2001 | Abandoned |
Array
(
[id] => 961111
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[patent_title] => 'Method for manufacturing a micromechanical component and a component that is manufactured in accordance with the method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/203729 | Method for manufacturing a micromechanical component and a component that is manufactured in accordance with the method | Dec 27, 2000 | Issued |
Array
(
[id] => 7040012
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[patent_title] => 'Organic electroluminescent device'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/735479 | Semiconductor device with dual damascene wiring | Dec 13, 2000 | Issued |
Array
(
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[patent_title] => 'Organic electroluminescent element'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/732909 | Organic electroluminescent element | Dec 10, 2000 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/718832 | Semiconductor device and method of manufacturing the same | Nov 21, 2000 | Issued |
Array
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 09652929
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652929 | Container capacitor structure and method of formation thereof | Aug 30, 2000 | Issued |