Search

Ginette Peralta

Examiner (ID: 9814)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1180526 [patent_doc_number] => 06744143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Semiconductor device having test mark' [patent_app_type] => B1 [patent_app_number] => 09/620718 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 3139 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744143.pdf [firstpage_image] =>[orig_patent_app_number] => 09620718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620718
Semiconductor device having test mark Jul 19, 2000 Issued
Array ( [id] => 1330490 [patent_doc_number] => 06600189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor device and semiconductor device manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/598379 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 80 [patent_no_of_words] => 13053 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600189.pdf [firstpage_image] =>[orig_patent_app_number] => 09598379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598379
Semiconductor device and semiconductor device manufacturing method Jun 20, 2000 Issued
Array ( [id] => 1221720 [patent_doc_number] => 06703668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Local interconnect formed using silicon spacer' [patent_app_type] => B1 [patent_app_number] => 09/588799 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3127 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703668.pdf [firstpage_image] =>[orig_patent_app_number] => 09588799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588799
Local interconnect formed using silicon spacer Jun 5, 2000 Issued
Array ( [id] => 1568371 [patent_doc_number] => 06376874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for fabricating a capacitor of a semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/584718 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2569 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376874.pdf [firstpage_image] =>[orig_patent_app_number] => 09584718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584718
Method for fabricating a capacitor of a semiconductor memory device May 31, 2000 Issued
Array ( [id] => 7645646 [patent_doc_number] => 06472323 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method of depositing tungsten nitride using a source gas comprising silicon' [patent_app_type] => B1 [patent_app_number] => 09/537238 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1611 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472323.pdf [firstpage_image] =>[orig_patent_app_number] => 09537238 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537238
Method of depositing tungsten nitride using a source gas comprising silicon Mar 27, 2000 Issued
Array ( [id] => 6934485 [patent_doc_number] => 20010055829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'METHOD OF MANUFACTURING AN IMAGE SENSOR' [patent_app_type] => new [patent_app_number] => 09/531940 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4632 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055829.pdf [firstpage_image] =>[orig_patent_app_number] => 09531940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531940
Method of manufacturing an image sensor Mar 20, 2000 Issued
Array ( [id] => 4381720 [patent_doc_number] => 06294464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Low resistance metal silicide local interconnects and a method of making' [patent_app_type] => 1 [patent_app_number] => 9/522086 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5714 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294464.pdf [firstpage_image] =>[orig_patent_app_number] => 522086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522086
Low resistance metal silicide local interconnects and a method of making Mar 9, 2000 Issued
09/520959 Semiconductor device and method of manufacturing same Mar 7, 2000 Abandoned
Array ( [id] => 1144470 [patent_doc_number] => 06777732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Random access memory' [patent_app_type] => B1 [patent_app_number] => 09/503638 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3837 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777732.pdf [firstpage_image] =>[orig_patent_app_number] => 09503638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503638
Random access memory Feb 13, 2000 Issued
Array ( [id] => 1190009 [patent_doc_number] => 06734562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Integrated circuit device structure including foamed polymeric material' [patent_app_type] => B1 [patent_app_number] => 09/480290 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6362 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734562.pdf [firstpage_image] =>[orig_patent_app_number] => 09480290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480290
Integrated circuit device structure including foamed polymeric material Jan 9, 2000 Issued
Array ( [id] => 1249089 [patent_doc_number] => 06674112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/446509 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 15865 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674112.pdf [firstpage_image] =>[orig_patent_app_number] => 09446509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/446509
Semiconductor integrated circuit device Dec 26, 1999 Issued
09/465928 SEMICONDUCTOR DEVICE CONTAINING OXIDE/NITRIDE/OXIDE DIELECTRIC LAYER NAD METHOD OF FORMING THE SAME Dec 16, 1999 Abandoned
Array ( [id] => 4423563 [patent_doc_number] => 06177698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Formation of controlled trench top isolation layers for vertical transistors' [patent_app_type] => 1 [patent_app_number] => 9/461599 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3794 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177698.pdf [firstpage_image] =>[orig_patent_app_number] => 461599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461599
Formation of controlled trench top isolation layers for vertical transistors Dec 14, 1999 Issued
Array ( [id] => 4405468 [patent_doc_number] => 06171881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Acceleration sensor and process for the production thereof' [patent_app_type] => 1 [patent_app_number] => 9/457349 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 7098 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171881.pdf [firstpage_image] =>[orig_patent_app_number] => 457349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457349
Acceleration sensor and process for the production thereof Dec 8, 1999 Issued
Array ( [id] => 6877233 [patent_doc_number] => 20010002719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => new-utility [patent_app_number] => 09/452099 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 9319 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002719.pdf [firstpage_image] =>[orig_patent_app_number] => 09452099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452099
SEMICONDUCTOR DEVICE Dec 1, 1999 Abandoned
Array ( [id] => 1509277 [patent_doc_number] => 06441418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Spacer narrowed, dual width contact for charge gain reduction' [patent_app_type] => B1 [patent_app_number] => 09/430848 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441418.pdf [firstpage_image] =>[orig_patent_app_number] => 09430848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430848
Spacer narrowed, dual width contact for charge gain reduction Oct 31, 1999 Issued
Array ( [id] => 4310308 [patent_doc_number] => 06326691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/429642 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 7927 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326691.pdf [firstpage_image] =>[orig_patent_app_number] => 429642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429642
Semiconductor device and method for manufacturing the same Oct 28, 1999 Issued
Array ( [id] => 1421131 [patent_doc_number] => 06509595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'DRAM cell fabricated using a modified logic process and method for operating same' [patent_app_type] => B1 [patent_app_number] => 09/427383 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 13615 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509595.pdf [firstpage_image] =>[orig_patent_app_number] => 09427383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427383
DRAM cell fabricated using a modified logic process and method for operating same Oct 24, 1999 Issued
Array ( [id] => 7643919 [patent_doc_number] => 06429119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Dual damascene process to reduce etch barrier thickness' [patent_app_type] => B1 [patent_app_number] => 09/405059 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4957 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429119.pdf [firstpage_image] =>[orig_patent_app_number] => 09405059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405059
Dual damascene process to reduce etch barrier thickness Sep 26, 1999 Issued
09/404538 SEMICONDUCTOR DEVICE WITH HIGH DRIVING FORCE AND LESS IMPURITY PUNCH-THROUGH AND METHOD OF MANUFACTURING THE SAME Sep 23, 1999 Abandoned
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