Search

Ginette Peralta

Examiner (ID: 17098)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
286
Issued Applications
235
Pending Applications
4
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1469906 [patent_doc_number] => 06406999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Semiconductor device having reduced line width variations between tightly spaced and isolated features' [patent_app_type] => B1 [patent_app_number] => 09/397459 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5220 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406999.pdf [firstpage_image] =>[orig_patent_app_number] => 09397459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397459
Semiconductor device having reduced line width variations between tightly spaced and isolated features Sep 15, 1999 Issued
Array ( [id] => 4358036 [patent_doc_number] => 06191029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Damascene process' [patent_app_type] => 1 [patent_app_number] => 9/392268 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191029.pdf [firstpage_image] =>[orig_patent_app_number] => 392268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392268
Damascene process Sep 8, 1999 Issued
Array ( [id] => 1267470 [patent_doc_number] => 06652604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Aluminum electrolytic capacitor and its manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/390709 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5944 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/652/06652604.pdf [firstpage_image] =>[orig_patent_app_number] => 09390709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390709
Aluminum electrolytic capacitor and its manufacturing method Sep 6, 1999 Issued
Array ( [id] => 4412733 [patent_doc_number] => 06239459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Capacitors, methods of forming capacitors and integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/393078 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2777 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239459.pdf [firstpage_image] =>[orig_patent_app_number] => 393078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393078
Capacitors, methods of forming capacitors and integrated circuitry Sep 6, 1999 Issued
Array ( [id] => 4214828 [patent_doc_number] => 06087192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Polymer marker' [patent_app_type] => 1 [patent_app_number] => 9/388728 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1683 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087192.pdf [firstpage_image] =>[orig_patent_app_number] => 388728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388728
Polymer marker Sep 1, 1999 Issued
Array ( [id] => 6141713 [patent_doc_number] => 20020001877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'INTERCONNECT FORMATION IN A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/388998 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1985 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001877.pdf [firstpage_image] =>[orig_patent_app_number] => 09388998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388998
INTERCONNECT FORMATION IN A SEMICONDUCTOR DEVICE Aug 31, 1999 Abandoned
Array ( [id] => 1476409 [patent_doc_number] => 06388324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Self-repairing interconnections for electrical circuits' [patent_app_type] => B2 [patent_app_number] => 09/386789 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388324.pdf [firstpage_image] =>[orig_patent_app_number] => 09386789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386789
Self-repairing interconnections for electrical circuits Aug 30, 1999 Issued
Array ( [id] => 1505882 [patent_doc_number] => 06440382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method for producing water for use in manufacturing semiconductors' [patent_app_type] => B1 [patent_app_number] => 09/387119 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4335 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440382.pdf [firstpage_image] =>[orig_patent_app_number] => 09387119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387119
Method for producing water for use in manufacturing semiconductors Aug 30, 1999 Issued
Array ( [id] => 1559788 [patent_doc_number] => 06361619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Thermally annealed wafers having improved internal gettering' [patent_app_type] => B1 [patent_app_number] => 09/385108 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10490 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/361/06361619.pdf [firstpage_image] =>[orig_patent_app_number] => 09385108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385108
Thermally annealed wafers having improved internal gettering Aug 26, 1999 Issued
Array ( [id] => 1585618 [patent_doc_number] => 06358841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of copper CMP on low dielectric constant HSQ material' [patent_app_type] => B1 [patent_app_number] => 09/379279 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358841.pdf [firstpage_image] =>[orig_patent_app_number] => 09379279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379279
Method of copper CMP on low dielectric constant HSQ material Aug 22, 1999 Issued
Array ( [id] => 1561208 [patent_doc_number] => 06362093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Dual damascene method employing sacrificial via fill layer' [patent_app_type] => B1 [patent_app_number] => 09/378459 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7231 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362093.pdf [firstpage_image] =>[orig_patent_app_number] => 09378459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378459
Dual damascene method employing sacrificial via fill layer Aug 19, 1999 Issued
Array ( [id] => 1410022 [patent_doc_number] => 06528414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Methods for forming wiring line structures in semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/376879 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5593 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528414.pdf [firstpage_image] =>[orig_patent_app_number] => 09376879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376879
Methods for forming wiring line structures in semiconductor devices Aug 17, 1999 Issued
Array ( [id] => 6141712 [patent_doc_number] => 20020001876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'METHOD OF MAKING AN INTEGRATED CIRCUIT DEVICE HAVING A PLANAR INTERLEVEL DIELECTRIC LAYER' [patent_app_type] => new [patent_app_number] => 09/376039 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2570 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001876.pdf [firstpage_image] =>[orig_patent_app_number] => 09376039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376039
METHOD OF MAKING AN INTEGRATED CIRCUIT DEVICE HAVING A PLANAR INTERLEVEL DIELECTRIC LAYER Aug 16, 1999 Abandoned
Array ( [id] => 1245746 [patent_doc_number] => 06677234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method of selectively forming silicide' [patent_app_type] => B1 [patent_app_number] => 09/369539 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2425 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677234.pdf [firstpage_image] =>[orig_patent_app_number] => 09369539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369539
Method of selectively forming silicide Aug 5, 1999 Issued
Array ( [id] => 1507482 [patent_doc_number] => 06440852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Integrated circuit including passivated copper interconnection lines and associated manufacturing methods' [patent_app_type] => B1 [patent_app_number] => 09/364858 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2703 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440852.pdf [firstpage_image] =>[orig_patent_app_number] => 09364858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364858
Integrated circuit including passivated copper interconnection lines and associated manufacturing methods Jul 29, 1999 Issued
Array ( [id] => 4246638 [patent_doc_number] => 06221700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities' [patent_app_type] => 1 [patent_app_number] => 9/362088 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4642 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221700.pdf [firstpage_image] =>[orig_patent_app_number] => 362088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362088
Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities Jul 27, 1999 Issued
Array ( [id] => 4354840 [patent_doc_number] => 06218319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method of forming an arsenic silicon glass film onto a silicon structure' [patent_app_type] => 1 [patent_app_number] => 9/362979 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218319.pdf [firstpage_image] =>[orig_patent_app_number] => 362979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362979
Method of forming an arsenic silicon glass film onto a silicon structure Jul 27, 1999 Issued
Array ( [id] => 4214552 [patent_doc_number] => 06110791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method of making a semiconductor variable capacitor' [patent_app_type] => 1 [patent_app_number] => 9/361348 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2960 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110791.pdf [firstpage_image] =>[orig_patent_app_number] => 361348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361348
Method of making a semiconductor variable capacitor Jul 25, 1999 Issued
Array ( [id] => 4294381 [patent_doc_number] => 06187088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Laser irradiation process' [patent_app_type] => 1 [patent_app_number] => 9/353358 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6641 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187088.pdf [firstpage_image] =>[orig_patent_app_number] => 353358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353358
Laser irradiation process Jul 14, 1999 Issued
Array ( [id] => 1407015 [patent_doc_number] => 06538308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor apparatus with heat radiation structure for removing heat from semiconductor element' [patent_app_type] => B1 [patent_app_number] => 09/351458 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 11209 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538308.pdf [firstpage_image] =>[orig_patent_app_number] => 09351458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351458
Semiconductor apparatus with heat radiation structure for removing heat from semiconductor element Jul 11, 1999 Issued
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