
Ginette Peralta
Examiner (ID: 17496)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 286 |
| Issued Applications | 235 |
| Pending Applications | 4 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1387253
[patent_doc_number] => 06555913
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Electronic component having a coil conductor with photosensitive conductive paste'
[patent_app_type] => B1
[patent_app_number] => 09/350038
[patent_app_country] => US
[patent_app_date] => 1999-07-08
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[pdf_file] => patents/06/555/06555913.pdf
[firstpage_image] =>[orig_patent_app_number] => 09350038
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350038 | Electronic component having a coil conductor with photosensitive conductive paste | Jul 7, 1999 | Issued |
Array
(
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[patent_doc_number] => 06351021
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Low temperature coefficient resistor (TCRL)'
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[patent_app_number] => 09/345929
[patent_app_country] => US
[patent_app_date] => 1999-07-01
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[firstpage_image] =>[orig_patent_app_number] => 09345929
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/345929 | Low temperature coefficient resistor (TCRL) | Jun 30, 1999 | Issued |
Array
(
[id] => 4258692
[patent_doc_number] => 06204152
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor'
[patent_app_type] => 1
[patent_app_number] => 9/340489
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[patent_app_date] => 1999-06-30
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[pdf_file] => patents/06/204/06204152.pdf
[firstpage_image] =>[orig_patent_app_number] => 340489
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340489 | Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor | Jun 29, 1999 | Issued |
Array
(
[id] => 4360480
[patent_doc_number] => 06218695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Area efficient column select circuitry for 2-bit non-volatile memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/340979
[patent_app_country] => US
[patent_app_date] => 1999-06-28
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[firstpage_image] =>[orig_patent_app_number] => 340979
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340979 | Area efficient column select circuitry for 2-bit non-volatile memory cells | Jun 27, 1999 | Issued |
Array
(
[id] => 4336531
[patent_doc_number] => 06333241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Method for fabricating capacitor of semiconductor memory device'
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[patent_app_country] => US
[patent_app_date] => 1999-06-24
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[firstpage_image] =>[orig_patent_app_number] => 339379
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339379 | Method for fabricating capacitor of semiconductor memory device | Jun 23, 1999 | Issued |
Array
(
[id] => 5951482
[patent_doc_number] => 20020006708
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[patent_kind] => A1
[patent_issue_date] => 2002-01-17
[patent_title] => 'METHOD OF FORMING SELECTIVE METAL LAYER AND METHOD OF FORMING CAPACITOR AND FILLING CONTACT HOLE USING THE SAME'
[patent_app_type] => new
[patent_app_number] => 09/334588
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[firstpage_image] =>[orig_patent_app_number] => 09334588
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/334588 | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same | Jun 15, 1999 | Issued |
Array
(
[id] => 1581195
[patent_doc_number] => 06423626
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[patent_issue_date] => 2002-07-23
[patent_title] => 'Removal of metal cusp for improved contact fill'
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[patent_app_number] => 09/334753
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[pdf_file] => patents/06/423/06423626.pdf
[firstpage_image] =>[orig_patent_app_number] => 09334753
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/334753 | Removal of metal cusp for improved contact fill | Jun 15, 1999 | Issued |
Array
(
[id] => 4325121
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[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source'
[patent_app_type] => 1
[patent_app_number] => 9/332059
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 332059
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/332059 | Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source | Jun 13, 1999 | Issued |
Array
(
[id] => 1421061
[patent_doc_number] => 06509589
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[patent_issue_date] => 2003-01-21
[patent_title] => 'Method and apparatus for compensating for ionizing radiation induced threshold shift in metal oxide semiconductor field transistors'
[patent_app_type] => B1
[patent_app_number] => 09/332599
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/332599 | Method and apparatus for compensating for ionizing radiation induced threshold shift in metal oxide semiconductor field transistors | Jun 13, 1999 | Issued |
Array
(
[id] => 4405244
[patent_doc_number] => 06271127
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[patent_issue_date] => 2001-08-07
[patent_title] => 'Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials'
[patent_app_type] => 1
[patent_app_number] => 9/329569
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/329569 | Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials | Jun 9, 1999 | Issued |
Array
(
[id] => 6395984
[patent_doc_number] => 20020036346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-28
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING DAMASCENE INTERCONNECTION STRUCTURE THAT PREVENTS VOID FORMATION BETWEEN INTERCONNECTIONS'
[patent_app_type] => new
[patent_app_number] => 09/329249
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/329249 | Semiconductor device having damascene interconnection structure that prevents void formation between interconnections | Jun 9, 1999 | Issued |
Array
(
[id] => 773485
[patent_doc_number] => 07001829
[patent_country] => US
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[patent_issue_date] => 2006-02-21
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
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Array
(
[id] => 4360495
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[patent_title] => 'Layout and wiring scheme for memory cells with vertical transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/326889 | Layout and wiring scheme for memory cells with vertical transistors | Jun 6, 1999 | Issued |
Array
(
[id] => 1576275
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[patent_title] => 'Non-volatile semiconductor memory device and manufacturing method thereof'
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Array
(
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[patent_title] => 'Method for fabricating a contact of a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/323889 | Method for fabricating a contact of a semiconductor device | Jun 1, 1999 | Issued |
Array
(
[id] => 1582907
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[patent_title] => 'Semiconductor device capacitor and method of manufacturing the same'
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/315329 | Process for producing metal-containing layers | May 19, 1999 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/313978 | Insulating film and method of forming the same | May 18, 1999 | Issued |