
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3716145
[patent_doc_number] => 05675743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Multi-media server'
[patent_app_type] => 1
[patent_app_number] => 8/392177
[patent_app_country] => US
[patent_app_date] => 1995-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5304
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675743.pdf
[firstpage_image] =>[orig_patent_app_number] => 392177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/392177 | Multi-media server | Feb 21, 1995 | Issued |
Array
(
[id] => 3742647
[patent_doc_number] => 05671443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Direct memory access acceleration device for use in a data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/391810
[patent_app_country] => US
[patent_app_date] => 1995-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7564
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/671/05671443.pdf
[firstpage_image] =>[orig_patent_app_number] => 391810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/391810 | Direct memory access acceleration device for use in a data processing system | Feb 20, 1995 | Issued |
Array
(
[id] => 3556653
[patent_doc_number] => 05555413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-10
[patent_title] => 'Computer system and method with integrated level and edge interrupt requests at the same interrupt priority'
[patent_app_type] => 1
[patent_app_number] => 8/390610
[patent_app_country] => US
[patent_app_date] => 1995-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 7884
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/555/05555413.pdf
[firstpage_image] =>[orig_patent_app_number] => 390610
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/390610 | Computer system and method with integrated level and edge interrupt requests at the same interrupt priority | Feb 16, 1995 | Issued |
Array
(
[id] => 3529693
[patent_doc_number] => 05506971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Method and apparatus for performing a snoop-retry protocol in a data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/386252
[patent_app_country] => US
[patent_app_date] => 1995-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3051
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506971.pdf
[firstpage_image] =>[orig_patent_app_number] => 386252
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/386252 | Method and apparatus for performing a snoop-retry protocol in a data processing system | Feb 8, 1995 | Issued |
Array
(
[id] => 3843699
[patent_doc_number] => 05712975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Input/output cell in parallel computer and parallel computer system'
[patent_app_type] => 1
[patent_app_number] => 8/381396
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 5716
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/712/05712975.pdf
[firstpage_image] =>[orig_patent_app_number] => 381396
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381396 | Input/output cell in parallel computer and parallel computer system | Jan 30, 1995 | Issued |
Array
(
[id] => 3566983
[patent_doc_number] => 05500946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-19
[patent_title] => 'Integrated dual bus controller'
[patent_app_type] => 1
[patent_app_number] => 8/380453
[patent_app_country] => US
[patent_app_date] => 1995-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2503
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/500/05500946.pdf
[firstpage_image] =>[orig_patent_app_number] => 380453
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/380453 | Integrated dual bus controller | Jan 26, 1995 | Issued |
Array
(
[id] => 3646641
[patent_doc_number] => 05632039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Circuit that automatically switches between supplying a microprocessor with a first voltage and a second voltage'
[patent_app_type] => 1
[patent_app_number] => 8/377151
[patent_app_country] => US
[patent_app_date] => 1995-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2754
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/632/05632039.pdf
[firstpage_image] =>[orig_patent_app_number] => 377151
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/377151 | Circuit that automatically switches between supplying a microprocessor with a first voltage and a second voltage | Jan 23, 1995 | Issued |
Array
(
[id] => 3759524
[patent_doc_number] => 05754881
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Method of controlling a PC parallel port switch for connecting multiple peripherals to the same parallel port'
[patent_app_type] => 1
[patent_app_number] => 8/378130
[patent_app_country] => US
[patent_app_date] => 1995-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4227
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754881.pdf
[firstpage_image] =>[orig_patent_app_number] => 378130
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378130 | Method of controlling a PC parallel port switch for connecting multiple peripherals to the same parallel port | Jan 23, 1995 | Issued |
| 08/367004 | COMPUTER REAL TIME CLOCK POWER SUPPLY CIRCUIT | Dec 29, 1994 | Abandoned |
Array
(
[id] => 3673128
[patent_doc_number] => 05592674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Automatic verification of external interrupts'
[patent_app_type] => 1
[patent_app_number] => 8/359810
[patent_app_country] => US
[patent_app_date] => 1994-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3861
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/592/05592674.pdf
[firstpage_image] =>[orig_patent_app_number] => 359810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/359810 | Automatic verification of external interrupts | Dec 19, 1994 | Issued |
Array
(
[id] => 3632275
[patent_doc_number] => 05642489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management'
[patent_app_type] => 1
[patent_app_number] => 8/359330
[patent_app_country] => US
[patent_app_date] => 1994-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 11499
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/642/05642489.pdf
[firstpage_image] =>[orig_patent_app_number] => 359330
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/359330 | Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management | Dec 18, 1994 | Issued |
Array
(
[id] => 3518609
[patent_doc_number] => 05515517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Data processing device with test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/357052
[patent_app_country] => US
[patent_app_date] => 1994-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5856
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/515/05515517.pdf
[firstpage_image] =>[orig_patent_app_number] => 357052
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357052 | Data processing device with test circuit | Dec 13, 1994 | Issued |
Array
(
[id] => 3626828
[patent_doc_number] => 05511205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'System for distributed power management in portable computers'
[patent_app_type] => 1
[patent_app_number] => 8/355205
[patent_app_country] => US
[patent_app_date] => 1994-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 17770
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/511/05511205.pdf
[firstpage_image] =>[orig_patent_app_number] => 355205
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/355205 | System for distributed power management in portable computers | Dec 7, 1994 | Issued |
| 08/347827 | INTERRUPT CONTROL METHOD FOR CONTROLLING AN INTERRUPT FROM A PERIPHERAL DEVICE TO A PROCESSOR | Nov 30, 1994 | Abandoned |
Array
(
[id] => 3709583
[patent_doc_number] => 05678064
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Local bus-ISA bridge for supporting PIO and third party DMA data transfers to IDE drives'
[patent_app_type] => 1
[patent_app_number] => 8/352131
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3822
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/678/05678064.pdf
[firstpage_image] =>[orig_patent_app_number] => 352131
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352131 | Local bus-ISA bridge for supporting PIO and third party DMA data transfers to IDE drives | Nov 30, 1994 | Issued |
Array
(
[id] => 3708217
[patent_doc_number] => 05619648
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Message filtering techniques'
[patent_app_type] => 1
[patent_app_number] => 8/346715
[patent_app_country] => US
[patent_app_date] => 1994-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 6100
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/619/05619648.pdf
[firstpage_image] =>[orig_patent_app_number] => 346715
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346715 | Message filtering techniques | Nov 29, 1994 | Issued |
Array
(
[id] => 3521577
[patent_doc_number] => 05588124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/351000
[patent_app_country] => US
[patent_app_date] => 1994-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7971
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/588/05588124.pdf
[firstpage_image] =>[orig_patent_app_number] => 351000
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/351000 | Microcomputer | Nov 28, 1994 | Issued |
Array
(
[id] => 3802819
[patent_doc_number] => 05737551
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Switching circuit for computer/data acquisition terminal'
[patent_app_type] => 1
[patent_app_number] => 8/345846
[patent_app_country] => US
[patent_app_date] => 1994-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2280
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/737/05737551.pdf
[firstpage_image] =>[orig_patent_app_number] => 345846
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/345846 | Switching circuit for computer/data acquisition terminal | Nov 27, 1994 | Issued |
Array
(
[id] => 3718402
[patent_doc_number] => 05655092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Multiple element interface'
[patent_app_type] => 1
[patent_app_number] => 8/344453
[patent_app_country] => US
[patent_app_date] => 1994-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5381
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/655/05655092.pdf
[firstpage_image] =>[orig_patent_app_number] => 344453
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/344453 | Multiple element interface | Nov 22, 1994 | Issued |
Array
(
[id] => 3561133
[patent_doc_number] => 05546550
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Method for assuring equal access to all input/output devices coupled to a SCSI bus'
[patent_app_type] => 1
[patent_app_number] => 8/344204
[patent_app_country] => US
[patent_app_date] => 1994-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3718
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/546/05546550.pdf
[firstpage_image] =>[orig_patent_app_number] => 344204
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/344204 | Method for assuring equal access to all input/output devices coupled to a SCSI bus | Nov 20, 1994 | Issued |