Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3585812 [patent_doc_number] => 05539910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Circuit configuration for monitoring the supply voltage of a processor unit' [patent_app_type] => 1 [patent_app_number] => 8/237379 [patent_app_country] => US [patent_app_date] => 1994-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2951 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539910.pdf [firstpage_image] =>[orig_patent_app_number] => 237379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237379
Circuit configuration for monitoring the supply voltage of a processor unit May 2, 1994 Issued
Array ( [id] => 3526277 [patent_doc_number] => 05513327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Integrated circuit I/O using a high performance bus interface' [patent_app_type] => 1 [patent_app_number] => 8/222646 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 15102 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513327.pdf [firstpage_image] =>[orig_patent_app_number] => 222646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/222646
Integrated circuit I/O using a high performance bus interface Mar 30, 1994 Issued
Array ( [id] => 3518918 [patent_doc_number] => 05515538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Apparatus and method for interrupt handling in a multi-threaded operating system kernel' [patent_app_type] => 1 [patent_app_number] => 8/219428 [patent_app_country] => US [patent_app_date] => 1994-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515538.pdf [firstpage_image] =>[orig_patent_app_number] => 219428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/219428
Apparatus and method for interrupt handling in a multi-threaded operating system kernel Mar 28, 1994 Issued
Array ( [id] => 3600621 [patent_doc_number] => 05553295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and apparatus for regulating the output voltage of negative charge pumps' [patent_app_type] => 1 [patent_app_number] => 8/217094 [patent_app_country] => US [patent_app_date] => 1994-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553295.pdf [firstpage_image] =>[orig_patent_app_number] => 217094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/217094
Method and apparatus for regulating the output voltage of negative charge pumps Mar 22, 1994 Issued
Array ( [id] => 3599981 [patent_doc_number] => 05497466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Universal address generator' [patent_app_type] => 1 [patent_app_number] => 8/210093 [patent_app_country] => US [patent_app_date] => 1994-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4276 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497466.pdf [firstpage_image] =>[orig_patent_app_number] => 210093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/210093
Universal address generator Mar 16, 1994 Issued
08/206275 POWER SAVING SYSTEM Mar 6, 1994 Abandoned
Array ( [id] => 3600877 [patent_doc_number] => 05550988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Apparatus and method for performing error correction in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/205604 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11446 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550988.pdf [firstpage_image] =>[orig_patent_app_number] => 205604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205604
Apparatus and method for performing error correction in a multi-processor system Feb 28, 1994 Issued
Array ( [id] => 3592771 [patent_doc_number] => 05499372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Method of controlling access to restricted access data and communication system therefor' [patent_app_type] => 1 [patent_app_number] => 8/202908 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2544 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499372.pdf [firstpage_image] =>[orig_patent_app_number] => 202908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202908
Method of controlling access to restricted access data and communication system therefor Feb 27, 1994 Issued
Array ( [id] => 3646628 [patent_doc_number] => 05632038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Secondary cache system for portable computer' [patent_app_type] => 1 [patent_app_number] => 8/199915 [patent_app_country] => US [patent_app_date] => 1994-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/632/05632038.pdf [firstpage_image] =>[orig_patent_app_number] => 199915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/199915
Secondary cache system for portable computer Feb 21, 1994 Issued
Array ( [id] => 3970283 [patent_doc_number] => 05991838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Motorized portable computer/expansion chassis docking system' [patent_app_type] => 1 [patent_app_number] => 8/164076 [patent_app_country] => US [patent_app_date] => 1994-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 15340 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991838.pdf [firstpage_image] =>[orig_patent_app_number] => 164076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/164076
Motorized portable computer/expansion chassis docking system Feb 16, 1994 Issued
Array ( [id] => 3502642 [patent_doc_number] => 05471674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Computer system with plug-in override of system ROM' [patent_app_type] => 1 [patent_app_number] => 8/197110 [patent_app_country] => US [patent_app_date] => 1994-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6117 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471674.pdf [firstpage_image] =>[orig_patent_app_number] => 197110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/197110
Computer system with plug-in override of system ROM Feb 15, 1994 Issued
Array ( [id] => 3547564 [patent_doc_number] => 05557757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus' [patent_app_type] => 1 [patent_app_number] => 8/190647 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4307 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557757.pdf [firstpage_image] =>[orig_patent_app_number] => 190647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/190647
High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus Feb 1, 1994 Issued
Array ( [id] => 3420076 [patent_doc_number] => 05438667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Method for data transmission and apparatus for implementation of this method' [patent_app_type] => 1 [patent_app_number] => 8/175689 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438667.pdf [firstpage_image] =>[orig_patent_app_number] => 175689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/175689
Method for data transmission and apparatus for implementation of this method Dec 29, 1993 Issued
Array ( [id] => 3518952 [patent_doc_number] => 05515540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Microprocessor with single pin for memory wipe' [patent_app_type] => 1 [patent_app_number] => 8/174584 [patent_app_country] => US [patent_app_date] => 1993-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14916 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515540.pdf [firstpage_image] =>[orig_patent_app_number] => 174584 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/174584
Microprocessor with single pin for memory wipe Dec 27, 1993 Issued
Array ( [id] => 3133555 [patent_doc_number] => 05450594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Enhanced collision detection for ethernet network' [patent_app_type] => 1 [patent_app_number] => 8/172489 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2976 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450594.pdf [firstpage_image] =>[orig_patent_app_number] => 172489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172489
Enhanced collision detection for ethernet network Dec 21, 1993 Issued
08/163757 PRINTING APPARATUS AND A METHOD THEREFOR, AND INFORMATION PROCESSING APPARATUS AND A METHOD THEREFOR Dec 8, 1993 Abandoned
08/162488 POWER MANAGEMENT OF DMA SLAVES WITH DMA TRAPS Dec 1, 1993 Abandoned
Array ( [id] => 3626733 [patent_doc_number] => 05511200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Method and apparatus for providing an enhanced programmable priority interrupt controller' [patent_app_type] => 1 [patent_app_number] => 8/160387 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4647 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511200.pdf [firstpage_image] =>[orig_patent_app_number] => 160387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/160387
Method and apparatus for providing an enhanced programmable priority interrupt controller Nov 30, 1993 Issued
Array ( [id] => 3471820 [patent_doc_number] => 05442755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Multi-processor system with lock address register in each processor for storing lock address sent to bus by another processor' [patent_app_type] => 1 [patent_app_number] => 8/144486 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4517 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442755.pdf [firstpage_image] =>[orig_patent_app_number] => 144486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/144486
Multi-processor system with lock address register in each processor for storing lock address sent to bus by another processor Oct 28, 1993 Issued
Array ( [id] => 3601245 [patent_doc_number] => 05517625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'System bus control system for multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/142918 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 8779 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517625.pdf [firstpage_image] =>[orig_patent_app_number] => 142918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/142918
System bus control system for multiprocessor system Oct 28, 1993 Issued
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