| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 3120260
[patent_doc_number] => 05418914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'Retry scheme for controlling transactions between two busses'
[patent_app_type] => 1
[patent_app_number] => 8/143393
[patent_app_country] => US
[patent_app_date] => 1993-10-25
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 143393
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/143393 | Retry scheme for controlling transactions between two busses | Oct 24, 1993 | Issued |
| 08/142884 | PORTABLE COMPUTER SYSTEM WITH ADAPTIVE POWER CONTROL PARAMETERS | Oct 24, 1993 | Abandoned |
Array
(
[id] => 3507296
[patent_doc_number] => 05509128
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'FPGA architecture including direct logic function circuit to I/O interconnections'
[patent_app_type] => 1
[patent_app_number] => 8/140724
[patent_app_country] => US
[patent_app_date] => 1993-10-20
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[firstpage_image] =>[orig_patent_app_number] => 140724
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/140724 | FPGA architecture including direct logic function circuit to I/O interconnections | Oct 19, 1993 | Issued |
Array
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[id] => 3502479
[patent_doc_number] => 05440697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Method and apparatus for simulating I/O devices'
[patent_app_type] => 1
[patent_app_number] => 8/138602
[patent_app_country] => US
[patent_app_date] => 1993-10-18
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[firstpage_image] =>[orig_patent_app_number] => 138602
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/138602 | Method and apparatus for simulating I/O devices | Oct 17, 1993 | Issued |
Array
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[id] => 3491305
[patent_doc_number] => 05457790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Low power consumption semiconductor integrated circuit device and microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/136990
[patent_app_country] => US
[patent_app_date] => 1993-10-18
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[firstpage_image] =>[orig_patent_app_number] => 136990
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/136990 | Low power consumption semiconductor integrated circuit device and microprocessor | Oct 17, 1993 | Issued |
Array
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[patent_doc_number] => 05355503
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[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Event driven scanning of data input equipment using multi-input wake-up techniques'
[patent_app_type] => 1
[patent_app_number] => 8/136475
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/136475 | Event driven scanning of data input equipment using multi-input wake-up techniques | Oct 12, 1993 | Issued |
Array
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[id] => 3473705
[patent_doc_number] => 05392435
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Microcomputer having a system clock frequency that varies in dependence on the number of nested and held interrupts'
[patent_app_type] => 1
[patent_app_number] => 8/129008
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[firstpage_image] =>[orig_patent_app_number] => 129008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/129008 | Microcomputer having a system clock frequency that varies in dependence on the number of nested and held interrupts | Sep 28, 1993 | Issued |
Array
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[id] => 3465063
[patent_doc_number] => 05379384
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Configuration data loopback in a bus bridge circuit'
[patent_app_type] => 1
[patent_app_number] => 8/126111
[patent_app_country] => US
[patent_app_date] => 1993-09-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/379/05379384.pdf
[firstpage_image] =>[orig_patent_app_number] => 126111
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/126111 | Configuration data loopback in a bus bridge circuit | Sep 22, 1993 | Issued |
Array
(
[id] => 3015583
[patent_doc_number] => 05371863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'High speed processor bus extension'
[patent_app_type] => 1
[patent_app_number] => 8/125620
[patent_app_country] => US
[patent_app_date] => 1993-09-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/371/05371863.pdf
[firstpage_image] =>[orig_patent_app_number] => 125620
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/125620 | High speed processor bus extension | Sep 21, 1993 | Issued |
Array
(
[id] => 3460919
[patent_doc_number] => 05386577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Display control apparatus capable of changing luminance depending on conditions of power supply circuit'
[patent_app_type] => 1
[patent_app_number] => 8/109476
[patent_app_country] => US
[patent_app_date] => 1993-08-20
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 109476
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/109476 | Display control apparatus capable of changing luminance depending on conditions of power supply circuit | Aug 19, 1993 | Issued |
| 08/109402 | BUS TERMINATING CIRCUIT | Aug 18, 1993 | Abandoned |
Array
(
[id] => 3126569
[patent_doc_number] => 05414859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Interprocessor communication protocol with built-in error prevention encoding'
[patent_app_type] => 1
[patent_app_number] => 8/106215
[patent_app_country] => US
[patent_app_date] => 1993-08-13
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[pdf_file] => patents/05/414/05414859.pdf
[firstpage_image] =>[orig_patent_app_number] => 106215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/106215 | Interprocessor communication protocol with built-in error prevention encoding | Aug 12, 1993 | Issued |
Array
(
[id] => 3123021
[patent_doc_number] => 05408668
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Method and apparatus for controlling the provision of power to computer peripherals'
[patent_app_type] => 1
[patent_app_number] => 8/098577
[patent_app_country] => US
[patent_app_date] => 1993-07-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/408/05408668.pdf
[firstpage_image] =>[orig_patent_app_number] => 098577
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/098577 | Method and apparatus for controlling the provision of power to computer peripherals | Jul 27, 1993 | Issued |
| 08/084963 | POWER SAVING SYSTEM | Jul 1, 1993 | Abandoned |
Array
(
[id] => 3460906
[patent_doc_number] => 05386576
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[patent_kind] => NA
[patent_issue_date] => 1995-01-31
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Array
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Array
(
[id] => 4025560
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[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Real-time power conservation for computers'
[patent_app_type] => 1
[patent_app_number] => 8/023831
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[firstpage_image] =>[orig_patent_app_number] => 023831
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/023831 | Real-time power conservation for computers | Apr 11, 1993 | Issued |
Array
(
[id] => 3537721
[patent_doc_number] => 05504908
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Power saving control system for computer system'
[patent_app_type] => 1
[patent_app_number] => 8/039869
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[firstpage_image] =>[orig_patent_app_number] => 039869
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/039869 | Power saving control system for computer system | Mar 29, 1993 | Issued |
| 08/030530 | POWER UP / POWER DOWN SYSTEM FOR ELECTRONIC HARDWARE WHICH CONSERVES ELECTRIC POWER | Mar 11, 1993 | Pending |
Array
(
[id] => 3434948
[patent_doc_number] => 05459840
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-17
[patent_title] => 'Input/output bus architecture with parallel arbitration'
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[firstpage_image] =>[orig_patent_app_number] => 023008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/023008 | Input/output bus architecture with parallel arbitration | Feb 25, 1993 | Issued |