Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3120260 [patent_doc_number] => 05418914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Retry scheme for controlling transactions between two busses' [patent_app_type] => 1 [patent_app_number] => 8/143393 [patent_app_country] => US [patent_app_date] => 1993-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2874 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418914.pdf [firstpage_image] =>[orig_patent_app_number] => 143393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/143393
Retry scheme for controlling transactions between two busses Oct 24, 1993 Issued
08/142884 PORTABLE COMPUTER SYSTEM WITH ADAPTIVE POWER CONTROL PARAMETERS Oct 24, 1993 Abandoned
Array ( [id] => 3507296 [patent_doc_number] => 05509128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'FPGA architecture including direct logic function circuit to I/O interconnections' [patent_app_type] => 1 [patent_app_number] => 8/140724 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3650 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/509/05509128.pdf [firstpage_image] =>[orig_patent_app_number] => 140724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/140724
FPGA architecture including direct logic function circuit to I/O interconnections Oct 19, 1993 Issued
Array ( [id] => 3502479 [patent_doc_number] => 05440697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Method and apparatus for simulating I/O devices' [patent_app_type] => 1 [patent_app_number] => 8/138602 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7417 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440697.pdf [firstpage_image] =>[orig_patent_app_number] => 138602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/138602
Method and apparatus for simulating I/O devices Oct 17, 1993 Issued
Array ( [id] => 3491305 [patent_doc_number] => 05457790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Low power consumption semiconductor integrated circuit device and microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/136990 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 11222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457790.pdf [firstpage_image] =>[orig_patent_app_number] => 136990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136990
Low power consumption semiconductor integrated circuit device and microprocessor Oct 17, 1993 Issued
Array ( [id] => 3021925 [patent_doc_number] => 05355503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Event driven scanning of data input equipment using multi-input wake-up techniques' [patent_app_type] => 1 [patent_app_number] => 8/136475 [patent_app_country] => US [patent_app_date] => 1993-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6159 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355503.pdf [firstpage_image] =>[orig_patent_app_number] => 136475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136475
Event driven scanning of data input equipment using multi-input wake-up techniques Oct 12, 1993 Issued
Array ( [id] => 3473705 [patent_doc_number] => 05392435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Microcomputer having a system clock frequency that varies in dependence on the number of nested and held interrupts' [patent_app_type] => 1 [patent_app_number] => 8/129008 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4210 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392435.pdf [firstpage_image] =>[orig_patent_app_number] => 129008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/129008
Microcomputer having a system clock frequency that varies in dependence on the number of nested and held interrupts Sep 28, 1993 Issued
Array ( [id] => 3465063 [patent_doc_number] => 05379384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Configuration data loopback in a bus bridge circuit' [patent_app_type] => 1 [patent_app_number] => 8/126111 [patent_app_country] => US [patent_app_date] => 1993-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3732 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379384.pdf [firstpage_image] =>[orig_patent_app_number] => 126111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/126111
Configuration data loopback in a bus bridge circuit Sep 22, 1993 Issued
Array ( [id] => 3015583 [patent_doc_number] => 05371863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'High speed processor bus extension' [patent_app_type] => 1 [patent_app_number] => 8/125620 [patent_app_country] => US [patent_app_date] => 1993-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6285 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371863.pdf [firstpage_image] =>[orig_patent_app_number] => 125620 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/125620
High speed processor bus extension Sep 21, 1993 Issued
Array ( [id] => 3460919 [patent_doc_number] => 05386577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Display control apparatus capable of changing luminance depending on conditions of power supply circuit' [patent_app_type] => 1 [patent_app_number] => 8/109476 [patent_app_country] => US [patent_app_date] => 1993-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3860 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386577.pdf [firstpage_image] =>[orig_patent_app_number] => 109476 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/109476
Display control apparatus capable of changing luminance depending on conditions of power supply circuit Aug 19, 1993 Issued
08/109402 BUS TERMINATING CIRCUIT Aug 18, 1993 Abandoned
Array ( [id] => 3126569 [patent_doc_number] => 05414859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Interprocessor communication protocol with built-in error prevention encoding' [patent_app_type] => 1 [patent_app_number] => 8/106215 [patent_app_country] => US [patent_app_date] => 1993-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414859.pdf [firstpage_image] =>[orig_patent_app_number] => 106215 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/106215
Interprocessor communication protocol with built-in error prevention encoding Aug 12, 1993 Issued
Array ( [id] => 3123021 [patent_doc_number] => 05408668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Method and apparatus for controlling the provision of power to computer peripherals' [patent_app_type] => 1 [patent_app_number] => 8/098577 [patent_app_country] => US [patent_app_date] => 1993-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5257 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408668.pdf [firstpage_image] =>[orig_patent_app_number] => 098577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/098577
Method and apparatus for controlling the provision of power to computer peripherals Jul 27, 1993 Issued
08/084963 POWER SAVING SYSTEM Jul 1, 1993 Abandoned
Array ( [id] => 3460906 [patent_doc_number] => 05386576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Method and apparatus for associating the reception of reset pulses by a microprocessor with access to different subprograms' [patent_app_type] => 1 [patent_app_number] => 8/049051 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2664 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386576.pdf [firstpage_image] =>[orig_patent_app_number] => 049051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049051
Method and apparatus for associating the reception of reset pulses by a microprocessor with access to different subprograms Apr 18, 1993 Issued
Array ( [id] => 3138977 [patent_doc_number] => 05437039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Servicing transparent system interrupts and reducing interrupt latency' [patent_app_type] => 1 [patent_app_number] => 8/047172 [patent_app_country] => US [patent_app_date] => 1993-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3142 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/437/05437039.pdf [firstpage_image] =>[orig_patent_app_number] => 047172 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/047172
Servicing transparent system interrupts and reducing interrupt latency Apr 12, 1993 Issued
Array ( [id] => 4025560 [patent_doc_number] => 06006336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Real-time power conservation for computers' [patent_app_type] => 1 [patent_app_number] => 8/023831 [patent_app_country] => US [patent_app_date] => 1993-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7212 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006336.pdf [firstpage_image] =>[orig_patent_app_number] => 023831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023831
Real-time power conservation for computers Apr 11, 1993 Issued
Array ( [id] => 3537721 [patent_doc_number] => 05504908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Power saving control system for computer system' [patent_app_type] => 1 [patent_app_number] => 8/039869 [patent_app_country] => US [patent_app_date] => 1993-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4116 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504908.pdf [firstpage_image] =>[orig_patent_app_number] => 039869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/039869
Power saving control system for computer system Mar 29, 1993 Issued
08/030530 POWER UP / POWER DOWN SYSTEM FOR ELECTRONIC HARDWARE WHICH CONSERVES ELECTRIC POWER Mar 11, 1993 Pending
Array ( [id] => 3434948 [patent_doc_number] => 05459840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Input/output bus architecture with parallel arbitration' [patent_app_type] => 1 [patent_app_number] => 8/023008 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16596 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459840.pdf [firstpage_image] =>[orig_patent_app_number] => 023008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023008
Input/output bus architecture with parallel arbitration Feb 25, 1993 Issued
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