Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
07/689329 DATA PROCESSING DEVICE WITH TEST CIRCUIT Apr 22, 1991 Abandoned
07/684890 A METHOD AND APPARATUS FOR CONTROLLING MEMORY ACCESS BY A CPU AND A SYSTEM BUS Apr 22, 1991 Abandoned
Array ( [id] => 3067135 [patent_doc_number] => 05345565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Multiple configuration data path architecture for a disk array controller' [patent_app_type] => 1 [patent_app_number] => 7/668660 [patent_app_country] => US [patent_app_date] => 1991-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 6064 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345565.pdf [firstpage_image] =>[orig_patent_app_number] => 668660 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/668660
Multiple configuration data path architecture for a disk array controller Mar 12, 1991 Issued
Array ( [id] => 2928156 [patent_doc_number] => 05179704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Method and apparatus for generating disk array interrupt signals' [patent_app_type] => 1 [patent_app_number] => 7/668641 [patent_app_country] => US [patent_app_date] => 1991-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3959 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179704.pdf [firstpage_image] =>[orig_patent_app_number] => 668641 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/668641
Method and apparatus for generating disk array interrupt signals Mar 12, 1991 Issued
07/665299 METHOD FOR BIDIRECTIONAL DATA TRANSMISSION IN A COMPUTER SYSTEM Mar 5, 1991 Abandoned
Array ( [id] => 2977653 [patent_doc_number] => 05274827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method for EEPROM write protection using threshold voltage projection' [patent_app_type] => 1 [patent_app_number] => 7/660628 [patent_app_country] => US [patent_app_date] => 1991-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1858 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274827.pdf [firstpage_image] =>[orig_patent_app_number] => 660628 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/660628
Method for EEPROM write protection using threshold voltage projection Feb 24, 1991 Issued
Array ( [id] => 3098529 [patent_doc_number] => 05285528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Data structures and algorithms for managing lock states of addressable element ranges' [patent_app_type] => 1 [patent_app_number] => 7/660451 [patent_app_country] => US [patent_app_date] => 1991-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 11880 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285528.pdf [firstpage_image] =>[orig_patent_app_number] => 660451 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/660451
Data structures and algorithms for managing lock states of addressable element ranges Feb 21, 1991 Issued
Array ( [id] => 3129639 [patent_doc_number] => 05410711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Portable computer with BIOS-independent power management' [patent_app_type] => 1 [patent_app_number] => 7/655889 [patent_app_country] => US [patent_app_date] => 1991-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 10923 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410711.pdf [firstpage_image] =>[orig_patent_app_number] => 655889 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655889
Portable computer with BIOS-independent power management Feb 13, 1991 Issued
Array ( [id] => 2989787 [patent_doc_number] => 05257357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method and apparatus for implementing a priority adjustment of an interrupt in a data processor' [patent_app_type] => 1 [patent_app_number] => 7/644142 [patent_app_country] => US [patent_app_date] => 1991-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2965 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257357.pdf [firstpage_image] =>[orig_patent_app_number] => 644142 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/644142
Method and apparatus for implementing a priority adjustment of an interrupt in a data processor Jan 21, 1991 Issued
07/639010 METHOD AND APPARATUS FOR ASSOCIATING THE RECEPTION OF RESET PULSES BY A MICROPROCESSOR WITH ACCESS TO DIFFERENT SUBPROGRAMS Jan 8, 1991 Abandoned
07/630860 MULTI-PROCESSOR SYSTEM WITH LOCK ADDRESS REGISTER IN EACH PROCESSOR FOR STORING LOCK ADDRESS SENT TO BUS BY ANOTHER PROCESSOR Dec 19, 1990 Abandoned
07/627847 LOW POWER CONSUMPTION SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MICROPROCESSOR Dec 13, 1990 Abandoned
Array ( [id] => 3064637 [patent_doc_number] => 05307464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Microprocessor and method for setting up its peripheral functions' [patent_app_type] => 1 [patent_app_number] => 7/621641 [patent_app_country] => US [patent_app_date] => 1990-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 48 [patent_no_of_words] => 28511 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307464.pdf [firstpage_image] =>[orig_patent_app_number] => 621641 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/621641
Microprocessor and method for setting up its peripheral functions Dec 2, 1990 Issued
Array ( [id] => 2933909 [patent_doc_number] => 05201036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Data processor having wait state control unit' [patent_app_type] => 1 [patent_app_number] => 7/619198 [patent_app_country] => US [patent_app_date] => 1990-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3648 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201036.pdf [firstpage_image] =>[orig_patent_app_number] => 619198 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/619198
Data processor having wait state control unit Nov 28, 1990 Issued
Array ( [id] => 3106993 [patent_doc_number] => 05313603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Arrangement of controlling memory access requests to grouped memory banks' [patent_app_type] => 1 [patent_app_number] => 7/606985 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2707 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313603.pdf [firstpage_image] =>[orig_patent_app_number] => 606985 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606985
Arrangement of controlling memory access requests to grouped memory banks Oct 30, 1990 Issued
Array ( [id] => 2977707 [patent_doc_number] => 05274830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Zero warranty circuit for data path having different bit width from the length of packed decimal operand' [patent_app_type] => 1 [patent_app_number] => 7/604270 [patent_app_country] => US [patent_app_date] => 1990-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1628 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274830.pdf [firstpage_image] =>[orig_patent_app_number] => 604270 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/604270
Zero warranty circuit for data path having different bit width from the length of packed decimal operand Oct 28, 1990 Issued
07/604838 WORKSTATION POWER MANAGEMENT BY PAGE PLACEMENT CONTROL Oct 28, 1990 Abandoned
Array ( [id] => 3035631 [patent_doc_number] => 05289583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Bus master with antilockup and no idle bus cycles' [patent_app_type] => 1 [patent_app_number] => 7/600337 [patent_app_country] => US [patent_app_date] => 1990-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4575 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289583.pdf [firstpage_image] =>[orig_patent_app_number] => 600337 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/600337
Bus master with antilockup and no idle bus cycles Oct 18, 1990 Issued
Array ( [id] => 3438780 [patent_doc_number] => 05404542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Power line switching circuit with monitor' [patent_app_type] => 1 [patent_app_number] => 7/600438 [patent_app_country] => US [patent_app_date] => 1990-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5151 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404542.pdf [firstpage_image] =>[orig_patent_app_number] => 600438 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/600438
Power line switching circuit with monitor Oct 18, 1990 Issued
Array ( [id] => 2934201 [patent_doc_number] => 05201051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Apparatus for interrupt detection and arbitration' [patent_app_type] => 1 [patent_app_number] => 7/590699 [patent_app_country] => US [patent_app_date] => 1990-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6202 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201051.pdf [firstpage_image] =>[orig_patent_app_number] => 590699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590699
Apparatus for interrupt detection and arbitration Sep 30, 1990 Issued
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