| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2946841
[patent_doc_number] => 05197143
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Device and method for distributing information in a computer system'
[patent_app_type] => 1
[patent_app_number] => 7/591088
[patent_app_country] => US
[patent_app_date] => 1990-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8640
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/197/05197143.pdf
[firstpage_image] =>[orig_patent_app_number] => 591088
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/591088 | Device and method for distributing information in a computer system | Sep 30, 1990 | Issued |
Array
(
[id] => 3094733
[patent_doc_number] => 05280585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Device sharing system using PCL macros'
[patent_app_type] => 1
[patent_app_number] => 7/590878
[patent_app_country] => US
[patent_app_date] => 1990-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2655
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/280/05280585.pdf
[firstpage_image] =>[orig_patent_app_number] => 590878
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/590878 | Device sharing system using PCL macros | Sep 27, 1990 | Issued |
Array
(
[id] => 2947756
[patent_doc_number] => 05247621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'System and method for processor bus use'
[patent_app_type] => 1
[patent_app_number] => 7/588194
[patent_app_country] => US
[patent_app_date] => 1990-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3542
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247621.pdf
[firstpage_image] =>[orig_patent_app_number] => 588194
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/588194 | System and method for processor bus use | Sep 25, 1990 | Issued |
Array
(
[id] => 2930607
[patent_doc_number] => 05193195
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-09
[patent_title] => 'Microcomputer having easily testable interrupt controller'
[patent_app_type] => 1
[patent_app_number] => 7/586789
[patent_app_country] => US
[patent_app_date] => 1990-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5943
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/193/05193195.pdf
[firstpage_image] =>[orig_patent_app_number] => 586789
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/586789 | Microcomputer having easily testable interrupt controller | Sep 20, 1990 | Issued |
Array
(
[id] => 2939557
[patent_doc_number] => 05187778
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-16
[patent_title] => 'Buffered disk unit and method of transferring data therein'
[patent_app_type] => 1
[patent_app_number] => 7/579718
[patent_app_country] => US
[patent_app_date] => 1990-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 42
[patent_no_of_words] => 13277
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/187/05187778.pdf
[firstpage_image] =>[orig_patent_app_number] => 579718
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/579718 | Buffered disk unit and method of transferring data therein | Sep 9, 1990 | Issued |
| 07/578247 | DISPLAY CONTROL APPARATUS CAPABLE OF CHANGING LUMINANCE DEPENDING ON CONDITIONS OF POWER SUPPLY CIRCUIT | Sep 5, 1990 | Abandoned |
Array
(
[id] => 2934238
[patent_doc_number] => 05201053
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-06
[patent_title] => 'Dynamic polling of devices for nonsynchronous channel connection'
[patent_app_type] => 1
[patent_app_number] => 7/576049
[patent_app_country] => US
[patent_app_date] => 1990-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 15571
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/201/05201053.pdf
[firstpage_image] =>[orig_patent_app_number] => 576049
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/576049 | Dynamic polling of devices for nonsynchronous channel connection | Aug 30, 1990 | Issued |
| 07/573585 | MICROPROCESSOR WITH SINGLE PIN FOR MEMORY WIPE | Aug 26, 1990 | Abandoned |
Array
(
[id] => 2850047
[patent_doc_number] => 05121491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-09
[patent_title] => 'MIDI to RS 232 interface'
[patent_app_type] => 1
[patent_app_number] => 7/571329
[patent_app_country] => US
[patent_app_date] => 1990-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2272
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/121/05121491.pdf
[firstpage_image] =>[orig_patent_app_number] => 571329
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/571329 | MIDI to RS 232 interface | Aug 21, 1990 | Issued |
Array
(
[id] => 2816249
[patent_doc_number] => 05125093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Interrupt control for multiprocessor computer system'
[patent_app_type] => 1
[patent_app_number] => 7/567399
[patent_app_country] => US
[patent_app_date] => 1990-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8001
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/125/05125093.pdf
[firstpage_image] =>[orig_patent_app_number] => 567399
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/567399 | Interrupt control for multiprocessor computer system | Aug 13, 1990 | Issued |
| 07/549278 | METHOD AND APPARATUS FOR CONTROLLING AND COMMUNICATING WITH BUSINESS OFFICE DEVICES | Jul 5, 1990 | Abandoned |
| 07/546601 | DISK DRIVER WITH LOOKAHEAD CACHE | Jun 28, 1990 | Abandoned |
Array
(
[id] => 2961487
[patent_doc_number] => 05222218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-22
[patent_title] => 'System with devices connected in sequence to receive information in a predetermined order'
[patent_app_type] => 1
[patent_app_number] => 7/544520
[patent_app_country] => US
[patent_app_date] => 1990-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4613
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/222/05222218.pdf
[firstpage_image] =>[orig_patent_app_number] => 544520
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/544520 | System with devices connected in sequence to receive information in a predetermined order | Jun 26, 1990 | Issued |
Array
(
[id] => 3089803
[patent_doc_number] => 05297261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Multiprocessor system with power-on reset function'
[patent_app_type] => 1
[patent_app_number] => 7/536758
[patent_app_country] => US
[patent_app_date] => 1990-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3353
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/297/05297261.pdf
[firstpage_image] =>[orig_patent_app_number] => 536758
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/536758 | Multiprocessor system with power-on reset function | Jun 11, 1990 | Issued |
Array
(
[id] => 2927453
[patent_doc_number] => 05179666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'Block oriented peripheral device interface'
[patent_app_type] => 1
[patent_app_number] => 7/534428
[patent_app_country] => US
[patent_app_date] => 1990-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 5490
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/179/05179666.pdf
[firstpage_image] =>[orig_patent_app_number] => 534428
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/534428 | Block oriented peripheral device interface | Jun 6, 1990 | Issued |
| 07/531318 | EVENT DRIVEN SCANNING OF DATA INPUT EQUIPMENT USING MULTI-INPUT WAKE- UP TECHNIQUES | May 30, 1990 | Abandoned |
Array
(
[id] => 2849899
[patent_doc_number] => 05121483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-09
[patent_title] => 'Virtual drives in an automated storage library'
[patent_app_type] => 1
[patent_app_number] => 7/525590
[patent_app_country] => US
[patent_app_date] => 1990-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 13160
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/121/05121483.pdf
[firstpage_image] =>[orig_patent_app_number] => 525590
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/525590 | Virtual drives in an automated storage library | May 20, 1990 | Issued |
Array
(
[id] => 2803753
[patent_doc_number] => 05136693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-04
[patent_title] => 'Architecture for a signal processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/524390
[patent_app_country] => US
[patent_app_date] => 1990-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1860
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/136/05136693.pdf
[firstpage_image] =>[orig_patent_app_number] => 524390
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/524390 | Architecture for a signal processing apparatus | May 16, 1990 | Issued |
| 07/510898 | INTEGRATED CIRCUIT I/O USING A HIGH PERFORMANCE BUS INTERFACE | Apr 17, 1990 | Abandoned |
Array
(
[id] => 2754904
[patent_doc_number] => 05012408
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Memory array addressing system for computer systems with multiple memory arrays'
[patent_app_type] => 1
[patent_app_number] => 7/494780
[patent_app_country] => US
[patent_app_date] => 1990-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5281
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012408.pdf
[firstpage_image] =>[orig_patent_app_number] => 494780
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/494780 | Memory array addressing system for computer systems with multiple memory arrays | Mar 14, 1990 | Issued |