Search

Glenn Allen Auve

Examiner (ID: 8999, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2111, 2186, 2308, 2781, 2305, 2175, 2181, 2185
Total Applications
2279
Issued Applications
2039
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16659423 [patent_doc_number] => 20210056060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => TRANSCEIVER AND DRIVER ARCHITECTURE WITH LOW EMISSION AND HIGH INTERFERENCE TOLERANCE [patent_app_type] => utility [patent_app_number] => 16/588562 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588562
Transceiver and driver architecture with low emission and high interference tolerance Sep 29, 2019 Issued
Array ( [id] => 15685483 [patent_doc_number] => 20200097405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => STORAGE SYSTEM WITH INTERCONNECTED SOLID STATE DISKS [patent_app_type] => utility [patent_app_number] => 16/585892 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585892
Storage system with interconnected solid state disks Sep 26, 2019 Issued
Array ( [id] => 16446462 [patent_doc_number] => 10838386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Distributed modular I/O device with configurable single-channel I/O submodules [patent_app_type] => utility [patent_app_number] => 16/584132 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4991 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584132 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584132
Distributed modular I/O device with configurable single-channel I/O submodules Sep 25, 2019 Issued
Array ( [id] => 16534953 [patent_doc_number] => 10877552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Dynamic power reduction through data transfer request limiting [patent_app_type] => utility [patent_app_number] => 16/575714 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575714
Dynamic power reduction through data transfer request limiting Sep 18, 2019 Issued
Array ( [id] => 16744867 [patent_doc_number] => 10969853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => USB adapting circuit [patent_app_type] => utility [patent_app_number] => 16/574675 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574675
USB adapting circuit Sep 17, 2019 Issued
Array ( [id] => 17001138 [patent_doc_number] => 11079948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Memory system for updating firmware when SPO occurs and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/569309 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6284 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569309
Memory system for updating firmware when SPO occurs and operating method thereof Sep 11, 2019 Issued
Array ( [id] => 16575494 [patent_doc_number] => 10897429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Managing multiple cartridges that are electrically coupled together [patent_app_type] => utility [patent_app_number] => 16/568917 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568917 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568917
Managing multiple cartridges that are electrically coupled together Sep 11, 2019 Issued
Array ( [id] => 16936172 [patent_doc_number] => 20210202061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYNCHRONIZING PHYSIOLOGICAL MEASUREMENT DATA STREAMS [patent_app_type] => utility [patent_app_number] => 17/267826 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17267826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/267826
Synchronizing physiological measurement data streams Sep 8, 2019 Issued
Array ( [id] => 15297171 [patent_doc_number] => 20190391721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD AND APPARATUS FOR RESPONDING TO TOUCH OPERATION, STORAGE MEDIUM AND TERMINAL [patent_app_type] => utility [patent_app_number] => 16/561805 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561805
Method and apparatus for responding to touch operation, storage medium and terminal Sep 4, 2019 Issued
Array ( [id] => 16675623 [patent_doc_number] => 20210064389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SOFTWARE COMPONENT CONFIGURATION ALIGNMENT [patent_app_type] => utility [patent_app_number] => 16/552262 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/552262
Software component configuration alignment Aug 26, 2019 Issued
Array ( [id] => 15459315 [patent_doc_number] => 20200042482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/543934 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543934
PCI express tunneling over a multi-protocol I/O interconnect Aug 18, 2019 Issued
Array ( [id] => 16644390 [patent_doc_number] => 10922247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Interface components [patent_app_type] => utility [patent_app_number] => 16/540594 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540594
Interface components Aug 13, 2019 Issued
Array ( [id] => 17861727 [patent_doc_number] => 11442885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => System and method to change field-programmable gate array personality from a baseboard management controller [patent_app_type] => utility [patent_app_number] => 16/537097 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537097 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537097
System and method to change field-programmable gate array personality from a baseboard management controller Aug 8, 2019 Issued
Array ( [id] => 16615487 [patent_doc_number] => 20210034140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT BASED SYSTEM MANAGEMENT BUS ISOLATION [patent_app_type] => utility [patent_app_number] => 16/524852 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524852
Power management integrated circuit based system management bus isolation Jul 28, 2019 Issued
Array ( [id] => 16608050 [patent_doc_number] => 10909055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => High performance interconnect physical layer [patent_app_type] => utility [patent_app_number] => 16/525454 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 21801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525454
High performance interconnect physical layer Jul 28, 2019 Issued
Array ( [id] => 15500543 [patent_doc_number] => 20200050460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SYSTEM AND METHOD OF DOWNLOADING A FIRMWARE TO A SERVER [patent_app_type] => utility [patent_app_number] => 16/520984 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520984
System and method of downloading a firmware to a server Jul 23, 2019 Issued
Array ( [id] => 16592661 [patent_doc_number] => 10901924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Mixing restartable and non-restartable requests with performance enhancements [patent_app_type] => utility [patent_app_number] => 16/520387 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6796 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520387
Mixing restartable and non-restartable requests with performance enhancements Jul 23, 2019 Issued
Array ( [id] => 16600116 [patent_doc_number] => 20210026647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => METHOD OF CONSTRUCTING A UEFI BOOTLOADER HANDOFF ADDRESS SPACE FOR A PHYSICAL MACHINE HOSTING VIRTUAL MACHINES [patent_app_type] => utility [patent_app_number] => 16/519867 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/519867
Constructing a UEFI bootloader handoff address space for a physical machine hosting virtual machines Jul 22, 2019 Issued
Array ( [id] => 15090685 [patent_doc_number] => 20190340153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/512551 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512551
Memory-based distributed processor architecture Jul 15, 2019 Issued
Array ( [id] => 15439949 [patent_doc_number] => 20200034158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => LOW LATENCY CLOCK-BASED CONTROL VIA SERIAL BUS [patent_app_type] => utility [patent_app_number] => 16/507947 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507947
Low latency clock-based control via serial bus Jul 9, 2019 Issued
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