Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11903528 [patent_doc_number] => 09772962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Memory sharing for direct memory access by a device assigned to a guest operating system' [patent_app_type] => utility [patent_app_number] => 14/724308 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724308
Memory sharing for direct memory access by a device assigned to a guest operating system May 27, 2015 Issued
Array ( [id] => 11027550 [patent_doc_number] => 20160224506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'INTERFACE CIRCUIT FOR HIGH SPEED COMMUNICATION, AND SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/724303 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724303
Interface circuit for high speed communication, and semiconductor apparatus and system including the same May 27, 2015 Issued
Array ( [id] => 11314124 [patent_doc_number] => 20160350235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'EXIT-LESS MOVEMENT OF GUEST MEMORY ASSIGNED TO A DEVICE IN A VIRTUALIZED ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/723183 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723183 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723183
Exit-less movement of guest memory assigned to a device in a virtualized environment May 26, 2015 Issued
Array ( [id] => 10486670 [patent_doc_number] => 20150371690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/722291 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722291
Time-constrained data copying between storage media May 26, 2015 Issued
Array ( [id] => 11910239 [patent_doc_number] => 09779050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Allocating virtual resources to root PCI bus' [patent_app_type] => utility [patent_app_number] => 14/697213 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697213 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697213
Allocating virtual resources to root PCI bus Apr 26, 2015 Issued
Array ( [id] => 10485723 [patent_doc_number] => 20150370743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'Interface for Bridging Out-of-Band Information from a Downstream Communication Link to an Upstream Communication Link' [patent_app_type] => utility [patent_app_number] => 14/691487 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7024 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691487
Interface for bridging out-of-band information from a downstream communication link to an upstream communication link Apr 19, 2015 Issued
Array ( [id] => 11109795 [patent_doc_number] => 20160306765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS' [patent_app_type] => utility [patent_app_number] => 14/689677 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14689677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/689677
Low power parallelization to multiple output bus widths Apr 16, 2015 Issued
Array ( [id] => 12352446 [patent_doc_number] => 09952991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation [patent_app_type] => utility [patent_app_number] => 14/690339 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8042 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690339 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/690339
Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation Apr 16, 2015 Issued
Array ( [id] => 10117696 [patent_doc_number] => 09152581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Chip storing a value that represents adjustment to output drive strength' [patent_app_type] => utility [patent_app_number] => 14/686522 [patent_app_country] => US [patent_app_date] => 2015-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 13033 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14686522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/686522
Chip storing a value that represents adjustment to output drive strength Apr 13, 2015 Issued
Array ( [id] => 10099652 [patent_doc_number] => 09135967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Chip having register to store value that represents adjustment to output drive strength' [patent_app_type] => utility [patent_app_number] => 14/683324 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 13033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683324 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683324
Chip having register to store value that represents adjustment to output drive strength Apr 9, 2015 Issued
Array ( [id] => 10327964 [patent_doc_number] => 20150212968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVER PARAMETER' [patent_app_type] => utility [patent_app_number] => 14/683290 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683290
Chip having port to receive value that represents adjustment to output driver parameter Apr 9, 2015 Issued
Array ( [id] => 10327950 [patent_doc_number] => 20150212954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO TRANSMISSION PARAMETER' [patent_app_type] => utility [patent_app_number] => 14/682926 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13032 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14682926 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/682926
Chip having port to receive value that represents adjustment to transmission parameter Apr 8, 2015 Issued
Array ( [id] => 12966772 [patent_doc_number] => 09875152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system [patent_app_type] => utility [patent_app_number] => 14/666116 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 103 [patent_no_of_words] => 18802 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/666116
Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system Mar 22, 2015 Issued
Array ( [id] => 11570537 [patent_doc_number] => 20170109181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/311543 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 19442 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15311543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/311543
Information processing apparatus including tags for controlling operation modes Mar 16, 2015 Issued
Array ( [id] => 10731844 [patent_doc_number] => 20160077994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'INTERFACE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/657281 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14657281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/657281
Interface circuit executing protocol control in compliance with first and second interface standards Mar 12, 2015 Issued
Array ( [id] => 10384102 [patent_doc_number] => 20150269109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRANSACTION LAYER PACKETS' [patent_app_type] => utility [patent_app_number] => 14/658026 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658026
Method, apparatus and system for single-ended communication of transaction layer packets Mar 12, 2015 Issued
Array ( [id] => 10816266 [patent_doc_number] => 20160162427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'INTEGRATED SYSTEMS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 14/645112 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/645112
Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity Mar 10, 2015 Issued
Array ( [id] => 10314292 [patent_doc_number] => 20150199295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'RECEIVE CLOCK CALIBRATION FOR A SERIAL BUS' [patent_app_type] => utility [patent_app_number] => 14/616572 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 25629 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616572 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/616572
Receive clock calibration for a serial bus Feb 5, 2015 Issued
Array ( [id] => 11584850 [patent_doc_number] => 09639492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Virtual PCI expander device' [patent_app_type] => utility [patent_app_number] => 14/597802 [patent_app_country] => US [patent_app_date] => 2015-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14597802 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/597802
Virtual PCI expander device Jan 14, 2015 Issued
Array ( [id] => 11860965 [patent_doc_number] => 09740648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Substrate treatment apparatus that controls respective units by master-slave method' [patent_app_type] => utility [patent_app_number] => 14/595263 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8121 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595263
Substrate treatment apparatus that controls respective units by master-slave method Jan 12, 2015 Issued
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