
Glenn Allen Auve
Examiner (ID: 8999)
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2111, 2186, 2308, 2781, 2305, 2175, 2181, 2185 |
| Total Applications | 2279 |
| Issued Applications | 2039 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12966772
[patent_doc_number] => 09875152
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-23
[patent_title] => Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system
[patent_app_type] => utility
[patent_app_number] => 14/666116
[patent_app_country] => US
[patent_app_date] => 2015-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 88
[patent_figures_cnt] => 103
[patent_no_of_words] => 18802
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666116
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/666116 | Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system | Mar 22, 2015 | Issued |
Array
(
[id] => 11570537
[patent_doc_number] => 20170109181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 15/311543
[patent_app_country] => US
[patent_app_date] => 2015-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 19442
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15311543
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/311543 | Information processing apparatus including tags for controlling operation modes | Mar 16, 2015 | Issued |
Array
(
[id] => 10384102
[patent_doc_number] => 20150269109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-24
[patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRANSACTION LAYER PACKETS'
[patent_app_type] => utility
[patent_app_number] => 14/658026
[patent_app_country] => US
[patent_app_date] => 2015-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8298
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658026
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/658026 | Method, apparatus and system for single-ended communication of transaction layer packets | Mar 12, 2015 | Issued |
Array
(
[id] => 10731844
[patent_doc_number] => 20160077994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-17
[patent_title] => 'INTERFACE CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 14/657281
[patent_app_country] => US
[patent_app_date] => 2015-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2248
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14657281
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/657281 | Interface circuit executing protocol control in compliance with first and second interface standards | Mar 12, 2015 | Issued |
Array
(
[id] => 10816266
[patent_doc_number] => 20160162427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'INTEGRATED SYSTEMS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY'
[patent_app_type] => utility
[patent_app_number] => 14/645112
[patent_app_country] => US
[patent_app_date] => 2015-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 18114
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645112
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/645112 | Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity | Mar 10, 2015 | Issued |
Array
(
[id] => 10314292
[patent_doc_number] => 20150199295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-16
[patent_title] => 'RECEIVE CLOCK CALIBRATION FOR A SERIAL BUS'
[patent_app_type] => utility
[patent_app_number] => 14/616572
[patent_app_country] => US
[patent_app_date] => 2015-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 63
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616572
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/616572 | Receive clock calibration for a serial bus | Feb 5, 2015 | Issued |
Array
(
[id] => 11584850
[patent_doc_number] => 09639492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-02
[patent_title] => 'Virtual PCI expander device'
[patent_app_type] => utility
[patent_app_number] => 14/597802
[patent_app_country] => US
[patent_app_date] => 2015-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5381
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14597802
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/597802 | Virtual PCI expander device | Jan 14, 2015 | Issued |
Array
(
[id] => 11860965
[patent_doc_number] => 09740648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Substrate treatment apparatus that controls respective units by master-slave method'
[patent_app_type] => utility
[patent_app_number] => 14/595263
[patent_app_country] => US
[patent_app_date] => 2015-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8121
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595263
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/595263 | Substrate treatment apparatus that controls respective units by master-slave method | Jan 12, 2015 | Issued |
Array
(
[id] => 11700810
[patent_doc_number] => 09690725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Camera control interface extension with in-band interrupt'
[patent_app_type] => utility
[patent_app_number] => 14/595030
[patent_app_country] => US
[patent_app_date] => 2015-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
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[patent_no_of_words] => 21464
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595030
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/595030 | Camera control interface extension with in-band interrupt | Jan 11, 2015 | Issued |
Array
(
[id] => 11006148
[patent_doc_number] => 20160203098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-14
[patent_title] => 'Enhanced Storage Option In Multi-slot Communications Supporting USB UICC SIM Cards'
[patent_app_type] => utility
[patent_app_number] => 14/593526
[patent_app_country] => US
[patent_app_date] => 2015-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 15394
[patent_no_of_claims] => 25
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593526
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/593526 | Enhanced storage option in multi-slot communications supporting USB UICC SIM cards | Jan 8, 2015 | Issued |
Array
(
[id] => 10999285
[patent_doc_number] => 20160196231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-07
[patent_title] => 'SYSTEM AND METHOD FOR BUS BANDWIDTH MANAGEMENT IN A SYSTEM ON A CHIP'
[patent_app_type] => utility
[patent_app_number] => 14/591749
[patent_app_country] => US
[patent_app_date] => 2015-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591749
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/591749 | SYSTEM AND METHOD FOR BUS BANDWIDTH MANAGEMENT IN A SYSTEM ON A CHIP | Jan 6, 2015 | Abandoned |
Array
(
[id] => 11830772
[patent_doc_number] => 09727514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity'
[patent_app_type] => utility
[patent_app_number] => 14/590780
[patent_app_country] => US
[patent_app_date] => 2015-01-06
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590780
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/590780 | Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity | Jan 5, 2015 | Issued |
Array
(
[id] => 11860971
[patent_doc_number] => 09740654
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Control messaging in multislot link layer flit'
[patent_app_type] => utility
[patent_app_number] => 14/583554
[patent_app_country] => US
[patent_app_date] => 2014-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583554
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/583554 | Control messaging in multislot link layer flit | Dec 25, 2014 | Issued |
Array
(
[id] => 10221550
[patent_doc_number] => 20150106543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'System and Method for Processing Device with Differentiated Execution Mode'
[patent_app_type] => utility
[patent_app_number] => 14/574356
[patent_app_country] => US
[patent_app_date] => 2014-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574356
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/574356 | System and method for processing device with differentiated execution mode | Dec 16, 2014 | Issued |
Array
(
[id] => 10824752
[patent_doc_number] => 20160170918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'FAULT TOLERANT LINK WIDTH MAXIMIZATION IN A DATA BUS'
[patent_app_type] => utility
[patent_app_number] => 14/571297
[patent_app_country] => US
[patent_app_date] => 2014-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571297
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/571297 | Fault tolerant link width maximization in a data bus | Dec 15, 2014 | Issued |
Array
(
[id] => 10824764
[patent_doc_number] => 20160170930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'Low cost low overhead serial interface for power management and other ICs'
[patent_app_type] => utility
[patent_app_number] => 14/570898
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14570898
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/570898 | Low cost low overhead serial interface for power management and other ICs | Dec 14, 2014 | Issued |
Array
(
[id] => 11752394
[patent_doc_number] => 09710406
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Data transmission using PCIe protocol via USB port'
[patent_app_type] => utility
[patent_app_number] => 14/570304
[patent_app_country] => US
[patent_app_date] => 2014-12-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/570304 | Data transmission using PCIe protocol via USB port | Dec 14, 2014 | Issued |
Array
(
[id] => 10827119
[patent_doc_number] => 20160173289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'PHYSICALLY UNCLONEABLE FUNCTION DEVICE USING MRAM'
[patent_app_type] => utility
[patent_app_number] => 14/570910
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/570910 | Physically uncloneable function device using MRAM | Dec 14, 2014 | Issued |
Array
(
[id] => 10824762
[patent_doc_number] => 20160170928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD HAVING MULTIPLE PCIe CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 14/569041
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/569041 | Peripheral component interconnect express (PCIe) card having multiple PCIe connectors | Dec 11, 2014 | Issued |
Array
(
[id] => 10210693
[patent_doc_number] => 20150095685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'DETACHABLE COMPUTER WITH VARIABLE PERFORMANCE COMPUTING ENVIRONMENT'
[patent_app_type] => utility
[patent_app_number] => 14/563892
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14563892
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/563892 | Detachable computer with variable performance computing environment | Dec 7, 2014 | Issued |