Search

Glenn Allen Auve

Examiner (ID: 8999)

Most Active Art Unit
2111
Art Unit(s)
2111, 2186, 2308, 2781, 2305, 2175, 2181, 2185
Total Applications
2279
Issued Applications
2039
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11786719 [patent_doc_number] => 09396154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Multi-core processor for managing data packets in communication network' [patent_app_type] => utility [patent_app_number] => 14/258046 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4792 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258046 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258046
Multi-core processor for managing data packets in communication network Apr 21, 2014 Issued
Array ( [id] => 11359206 [patent_doc_number] => 09535859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Sharing message-signaled interrupts between peripheral component interconnect (PCI) I/O devices' [patent_app_type] => utility [patent_app_number] => 14/254995 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7496 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/254995
Sharing message-signaled interrupts between peripheral component interconnect (PCI) I/O devices Apr 16, 2014 Issued
Array ( [id] => 11423263 [patent_doc_number] => 20170031407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'A CURRENT CONTROL CIRCUIT AND A METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/303244 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15303244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/303244
Current control circuit and a method therefor Apr 10, 2014 Issued
Array ( [id] => 10401591 [patent_doc_number] => 20150286600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'ARBITRATION MONITORING FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE SYSTEMS DURING DISCOVERY' [patent_app_type] => utility [patent_app_number] => 14/248171 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248171
Arbitration monitoring for serial attached small computer system interface systems during discovery Apr 7, 2014 Issued
Array ( [id] => 10392928 [patent_doc_number] => 20150277935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'TECHNIQUES FOR ADAPTIVE INTERFACE SUPPORT' [patent_app_type] => utility [patent_app_number] => 14/229870 [patent_app_country] => US [patent_app_date] => 2014-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14025 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229870
Techniques for adaptive interface support Mar 28, 2014 Issued
Array ( [id] => 10376577 [patent_doc_number] => 20150261584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'COALESCING STAGES IN A MULTIPLE STAGE COMPLETION SEQUENCE' [patent_app_type] => utility [patent_app_number] => 14/211167 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14211167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/211167
Coalescing stages in a multiple stage completion sequence Mar 13, 2014 Issued
Array ( [id] => 11416761 [patent_doc_number] => 09563588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'OS bypass inter-processor interrupt delivery mechanism' [patent_app_type] => utility [patent_app_number] => 14/208644 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/208644
OS bypass inter-processor interrupt delivery mechanism Mar 12, 2014 Issued
Array ( [id] => 11345343 [patent_doc_number] => 09529749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Data bus inversion (DBI) encoding based on the speed of operation' [patent_app_type] => utility [patent_app_number] => 14/202783 [patent_app_country] => US [patent_app_date] => 2014-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6460 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14202783 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/202783
Data bus inversion (DBI) encoding based on the speed of operation Mar 9, 2014 Issued
Array ( [id] => 9563853 [patent_doc_number] => 20140181566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND POWER SUPPLY CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/190394 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190394
Information processing apparatus and power supply control circuit Feb 25, 2014 Issued
Array ( [id] => 10249922 [patent_doc_number] => 20150134918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SINGLE INPUT/OUTPUT CELL WITH MULTIPLE BOND PADS AND/OR TRANSMITTERS' [patent_app_type] => utility [patent_app_number] => 14/191097 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7311 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191097 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/191097
Single input/output cell with multiple bond pads and/or transmitters Feb 25, 2014 Issued
Array ( [id] => 9563623 [patent_doc_number] => 20140181336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD, APPARATUS AND CABLE FOR ENABLING TWO TYPES OF HDMI COMMUNICATION' [patent_app_type] => utility [patent_app_number] => 14/189292 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15408 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189292
Method, apparatus and cable for enabling two types of HDMI communication Feb 24, 2014 Issued
Array ( [id] => 13120507 [patent_doc_number] => 10078607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Buffer management method and apparatus for universal serial bus communication in wireless environment [patent_app_type] => utility [patent_app_number] => 15/033841 [patent_app_country] => US [patent_app_date] => 2014-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5606 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033841
Buffer management method and apparatus for universal serial bus communication in wireless environment Feb 12, 2014 Issued
Array ( [id] => 10059297 [patent_doc_number] => 09098659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Advanced array local clock buffer base block circuit' [patent_app_type] => utility [patent_app_number] => 14/159570 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4864 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159570
Advanced array local clock buffer base block circuit Jan 20, 2014 Issued
Array ( [id] => 9871484 [patent_doc_number] => 08959276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Byte selection and steering logic for combined byte shift and byte permute vector unit' [patent_app_type] => utility [patent_app_number] => 14/148968 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3908 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148968
Byte selection and steering logic for combined byte shift and byte permute vector unit Jan 6, 2014 Issued
Array ( [id] => 10164631 [patent_doc_number] => 09195856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Data processing lock signal transmission' [patent_app_type] => utility [patent_app_number] => 14/074626 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10065 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074626
Data processing lock signal transmission Nov 6, 2013 Issued
Array ( [id] => 9688104 [patent_doc_number] => 20140244868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'INTEGRATED CIRCUIT DEVICES, SYSTEMS AND METHODS HAVING AUTOMATIC CONFIGURABLE MAPPING OF INPUT AND/OR OUTPUT DATA CONNECTIONS' [patent_app_type] => utility [patent_app_number] => 14/069590 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069590
Integrated circuit devices, systems and methods having automatic configurable mapping of input and/or output data connections Oct 31, 2013 Issued
Array ( [id] => 11739158 [patent_doc_number] => 09703741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Connector with a termination module' [patent_app_type] => utility [patent_app_number] => 14/390807 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5976 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14390807 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/390807
Connector with a termination module Oct 30, 2013 Issued
Array ( [id] => 9919106 [patent_doc_number] => 20150074311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'SIGNAL INTERRUPTS IN A TRANSACTIONAL MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/068214 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7845 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068214
Signal interrupts in a transactional memory system Oct 30, 2013 Issued
Array ( [id] => 10446399 [patent_doc_number] => 20150331413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'Method for Operating a Fieldbus Protocol Capable Field Device' [patent_app_type] => utility [patent_app_number] => 14/647716 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3213 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14647716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/647716
Method for operating a fieldbus protocol capable field device Oct 28, 2013 Issued
Array ( [id] => 10228191 [patent_doc_number] => 20150113184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'PROCESSOR COMMUNICATIONS' [patent_app_type] => utility [patent_app_number] => 14/059127 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13295 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059127
Interface between a bus and a inter-thread interconnect Oct 20, 2013 Issued
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