Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10536305 [patent_doc_number] => 09261933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Integrating energy budgets for power management' [patent_app_type] => utility [patent_app_number] => 13/858804 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858804 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858804
Integrating energy budgets for power management Apr 7, 2013 Issued
Array ( [id] => 10173052 [patent_doc_number] => 09203772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Managing multiple cartridges that are electrically coupled together' [patent_app_type] => utility [patent_app_number] => 13/855986 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855986 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855986
Managing multiple cartridges that are electrically coupled together Apr 2, 2013 Issued
Array ( [id] => 9006089 [patent_doc_number] => 20130227214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Chip Having Register to Store Value that Represents Adjustment to Reference Voltage' [patent_app_type] => utility [patent_app_number] => 13/853978 [patent_app_country] => US [patent_app_date] => 2013-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12997 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13853978 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/853978
Chip having register to store value that represents adjustment to reference voltage Mar 28, 2013 Issued
Array ( [id] => 9578745 [patent_doc_number] => 08769181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Multi-port system and method for routing a data element within an interconnection fabric' [patent_app_type] => utility [patent_app_number] => 13/846515 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846515
Multi-port system and method for routing a data element within an interconnection fabric Mar 17, 2013 Issued
Array ( [id] => 9437301 [patent_doc_number] => 20140115208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'CONTROL MESSAGING IN MULTISLOT LINK LAYER FLIT' [patent_app_type] => utility [patent_app_number] => 13/976966 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14588 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976966 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976966
Control messaging in multislot link layer flit Mar 14, 2013 Issued
Array ( [id] => 10188890 [patent_doc_number] => 09218310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Shared input/output (I/O) unit' [patent_app_type] => utility [patent_app_number] => 13/835000 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835000 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835000
Shared input/output (I/O) unit Mar 14, 2013 Issued
Array ( [id] => 11186631 [patent_doc_number] => 09418035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'High performance interconnect physical layer' [patent_app_type] => utility [patent_app_number] => 13/976960 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 22359 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976960
High performance interconnect physical layer Mar 14, 2013 Issued
Array ( [id] => 9758733 [patent_doc_number] => 20140289434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'Leveraging an Enumeration and/or Configuration Mechanism of One Interconnect Protocol for a Different Interconnect Protocol' [patent_app_type] => utility [patent_app_number] => 13/976548 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15013 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976548 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976548
Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol Feb 27, 2013 Issued
Array ( [id] => 9688113 [patent_doc_number] => 20140244878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Methods And Systems For Address Mapping Between Host And Expansion Devices Within System-In-Package (SiP) Solutions' [patent_app_type] => utility [patent_app_number] => 13/775313 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8757 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775313
Methods and systems for address mapping between host and expansion devices within system-in-package (SiP) solutions Feb 24, 2013 Issued
Array ( [id] => 9688108 [patent_doc_number] => 20140244873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Methods And Systems For Interconnecting Host And Expansion Devices Within System-In-Package (SiP) Solutions' [patent_app_type] => utility [patent_app_number] => 13/775330 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8968 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775330
Methods and systems for interconnecting host and expansion devices within system-in-package (SiP) solutions Feb 24, 2013 Issued
Array ( [id] => 10164630 [patent_doc_number] => 09195855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Data processing lock signal transmission' [patent_app_type] => utility [patent_app_number] => 13/774865 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10031 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774865 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774865
Data processing lock signal transmission Feb 21, 2013 Issued
Array ( [id] => 9006066 [patent_doc_number] => 20130227191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Image Forming Apparatus' [patent_app_type] => utility [patent_app_number] => 13/774592 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774592 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774592
Image forming apparatus performing arbitration of access requests from an IC chip to a memory Feb 21, 2013 Issued
Array ( [id] => 9688103 [patent_doc_number] => 20140244869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Dual Mode USB and Serial Console Port' [patent_app_type] => utility [patent_app_number] => 13/774713 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774713 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774713
Dual mode USB and serial console port Feb 21, 2013 Issued
Array ( [id] => 10507663 [patent_doc_number] => 09235538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Injecting interrupts in virtualized computer systems' [patent_app_type] => utility [patent_app_number] => 13/761874 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761874
Injecting interrupts in virtualized computer systems Feb 6, 2013 Issued
Array ( [id] => 8868041 [patent_doc_number] => 20130151744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Interrupt Moderation' [patent_app_type] => utility [patent_app_number] => 13/762077 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762077 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762077
Interrupt moderation Feb 6, 2013 Issued
Array ( [id] => 8886394 [patent_doc_number] => 20130159578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'System and method for Automatic Hardware Interrupt Handling' [patent_app_type] => utility [patent_app_number] => 13/758163 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 90 [patent_no_of_words] => 6204 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758163
System and method for Automatic Hardware Interrupt Handling Feb 3, 2013 Abandoned
Array ( [id] => 9416781 [patent_doc_number] => 08700833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Data storage device with host-accessible indicator' [patent_app_type] => utility [patent_app_number] => 13/743072 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743072
Data storage device with host-accessible indicator Jan 15, 2013 Issued
Array ( [id] => 9599033 [patent_doc_number] => 20140195714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'METHODS AND STRUCTURE FOR BUFFERING HOST REQUESTS IN SERIAL ATTACHED SCSI EXPANDERS' [patent_app_type] => utility [patent_app_number] => 13/734099 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734099
Methods and structure for buffering host requests in serial attached SCSI expanders Jan 3, 2013 Issued
Array ( [id] => 9571464 [patent_doc_number] => 20140189177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'HIGH SPEED OVERLAY OF IDLE I2C BUS BANDWIDTH' [patent_app_type] => utility [patent_app_number] => 13/733177 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733177 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733177
High speed overlay of idle I2C bus bandwidth Jan 2, 2013 Issued
Array ( [id] => 9571460 [patent_doc_number] => 20140189173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Network Efficiency and Power Savings' [patent_app_type] => utility [patent_app_number] => 13/733542 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5873 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733542
Network efficiency and power savings Jan 2, 2013 Issued
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