Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8697444 [patent_doc_number] => 20130059453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/666435 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2802 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/666435
Integrated circuits for accessing USB device Oct 31, 2012 Issued
Array ( [id] => 9123668 [patent_doc_number] => 20130290590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'CONNECTOR ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 13/663583 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 953 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663583
CONNECTOR ASSEMBLY Oct 29, 2012 Abandoned
Array ( [id] => 10041200 [patent_doc_number] => 09081907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Operating M-PHY based communications over peripheral component interconnect (PCI)-based interfaces, and related cables, connectors, systems and methods' [patent_app_type] => utility [patent_app_number] => 13/662999 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9094 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662999
Operating M-PHY based communications over peripheral component interconnect (PCI)-based interfaces, and related cables, connectors, systems and methods Oct 28, 2012 Issued
Array ( [id] => 9974136 [patent_doc_number] => 09021173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'High speed differential wiring strategy for serially attached SCSI systems' [patent_app_type] => utility [patent_app_number] => 13/661391 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4631 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661391
High speed differential wiring strategy for serially attached SCSI systems Oct 25, 2012 Issued
Array ( [id] => 10841117 [patent_doc_number] => 08868815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Information processing device and method' [patent_app_type] => utility [patent_app_number] => 13/661130 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5720 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661130
Information processing device and method Oct 25, 2012 Issued
Array ( [id] => 8794118 [patent_doc_number] => 20130111087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'METHOD AND A BUS DEVICE FOR TRANSMITTING SAFETY-ORIENTED DATA' [patent_app_type] => utility [patent_app_number] => 13/661698 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2251 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661698
Method and a bus device for transmitting safety-oriented data Oct 25, 2012 Issued
Array ( [id] => 9451590 [patent_doc_number] => 20140122760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS' [patent_app_type] => utility [patent_app_number] => 13/661456 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4508 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661456
Communication of message signalled interrupts Oct 25, 2012 Issued
Array ( [id] => 10854061 [patent_doc_number] => 08880771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Method and apparatus for securing and segregating host to host messaging on PCIe fabric' [patent_app_type] => utility [patent_app_number] => 13/660791 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4169 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660791
Method and apparatus for securing and segregating host to host messaging on PCIe fabric Oct 24, 2012 Issued
Array ( [id] => 8781894 [patent_doc_number] => 20130103869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/659183 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659183 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659183
Bus connection circuit, semiconductor device and operation method of bus connection circuit for making procedure for switching between a 1-cycle transfer and a 2-cycle transfer unnecessary Oct 23, 2012 Issued
Array ( [id] => 9940641 [patent_doc_number] => 08990472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Methods and systems for running network protocols over peripheral component interconnect express' [patent_app_type] => utility [patent_app_number] => 13/658976 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3657 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658976 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658976
Methods and systems for running network protocols over peripheral component interconnect express Oct 23, 2012 Issued
Array ( [id] => 9891520 [patent_doc_number] => 08977795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-10 [patent_title] => 'Method and apparatus for preventing multiple threads of a processor from accessing, in parallel, predetermined sections of source code' [patent_app_type] => utility [patent_app_number] => 13/658177 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658177 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658177
Method and apparatus for preventing multiple threads of a processor from accessing, in parallel, predetermined sections of source code Oct 22, 2012 Issued
Array ( [id] => 9410102 [patent_doc_number] => 20140101354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'MEMORY ACCESS CONTROL MODULE AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/647971 [patent_app_country] => US [patent_app_date] => 2012-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13647971 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/647971
Memory access control module and associated methods Oct 8, 2012 Issued
Array ( [id] => 8757009 [patent_doc_number] => 20130091314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'Field Bus Network Adapter and Field Bus Network Subscriber with Field Bus Connections' [patent_app_type] => utility [patent_app_number] => 13/646826 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2820 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646826 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646826
Field bus network adapter and field bus network subscriber with field bus connections Oct 7, 2012 Issued
Array ( [id] => 9410106 [patent_doc_number] => 20140101358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'BYTE SELECTION AND STEERING LOGIC FOR COMBINED BYTE SHIFT AND BYTE PERMUTE VECTOR UNIT' [patent_app_type] => utility [patent_app_number] => 13/646974 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3872 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646974 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646974
Byte selection and steering logic for combined byte shift and byte permute vector unit Oct 7, 2012 Issued
Array ( [id] => 9410100 [patent_doc_number] => 20140101352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'INTERRUPT CONTROLLER, APPARATUS INCLUDING INTERRUPT CONTROLLER, AND CORRESPONDING METHODS FOR PROCESSING INTERRUPT REQUEST EVENT(S) IN SYSTEM INCLUDING PROCESSOR(S)' [patent_app_type] => utility [patent_app_number] => 13/647365 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8755 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13647365 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/647365
Interrupt controller, apparatus including interrupt controller, and corresponding methods for processing interrupt request event(s) in system including processor(s) Oct 7, 2012 Issued
Array ( [id] => 9083178 [patent_doc_number] => 20130268708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'MOTHERBOARD TEST DEVICE AND CONNECTION MODULE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/646823 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646823 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646823
MOTHERBOARD TEST DEVICE AND CONNECTION MODULE THEREOF Oct 7, 2012 Abandoned
Array ( [id] => 9940633 [patent_doc_number] => 08990464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system' [patent_app_type] => utility [patent_app_number] => 13/646382 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 98 [patent_no_of_words] => 19422 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646382
Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system Oct 4, 2012 Issued
Array ( [id] => 9871476 [patent_doc_number] => 08959268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Information processing apparatus, serial communication system, method of initialization of communication therefor and serial communication apparatus' [patent_app_type] => utility [patent_app_number] => 13/646103 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7408 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646103
Information processing apparatus, serial communication system, method of initialization of communication therefor and serial communication apparatus Oct 4, 2012 Issued
Array ( [id] => 10885438 [patent_doc_number] => 08909841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Configurable serial interface' [patent_app_type] => utility [patent_app_number] => 13/645322 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5065 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645322
Configurable serial interface Oct 3, 2012 Issued
Array ( [id] => 10052376 [patent_doc_number] => 09092255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multi-core processor system, computer product, and control method for interrupt execution' [patent_app_type] => utility [patent_app_number] => 13/628709 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628709
Multi-core processor system, computer product, and control method for interrupt execution Sep 26, 2012 Issued
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