Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10052376 [patent_doc_number] => 09092255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multi-core processor system, computer product, and control method for interrupt execution' [patent_app_type] => utility [patent_app_number] => 13/628709 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628709
Multi-core processor system, computer product, and control method for interrupt execution Sep 26, 2012 Issued
Array ( [id] => 10105647 [patent_doc_number] => 09141429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Multicore processor system, computer product, and control method' [patent_app_type] => utility [patent_app_number] => 13/624353 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6810 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624353 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/624353
Multicore processor system, computer product, and control method Sep 20, 2012 Issued
Array ( [id] => 10072374 [patent_doc_number] => 09110733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Multi-core processor system, arbiter circuit control method, and computer product' [patent_app_type] => utility [patent_app_number] => 13/613634 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10729 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613634 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/613634
Multi-core processor system, arbiter circuit control method, and computer product Sep 12, 2012 Issued
Array ( [id] => 10052394 [patent_doc_number] => 09092273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multicore processor system, computer product, and control method' [patent_app_type] => utility [patent_app_number] => 13/614097 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9434 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614097 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/614097
Multicore processor system, computer product, and control method Sep 12, 2012 Issued
Array ( [id] => 9332479 [patent_doc_number] => 20140059261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'NOVEL LOCK LEASING METHOD FOR SOLVING DEADLOCK' [patent_app_type] => utility [patent_app_number] => 13/592282 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/592282
Lock leasing method for solving deadlock Aug 21, 2012 Issued
Array ( [id] => 9926215 [patent_doc_number] => 08984200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Task scheduling in big and little cores' [patent_app_type] => utility [patent_app_number] => 13/590484 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4890 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590484
Task scheduling in big and little cores Aug 20, 2012 Issued
Array ( [id] => 8517920 [patent_doc_number] => 20120317328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/590936 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590936 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590936
Scalable distributed memory and I/O multiprocessor system Aug 20, 2012 Issued
Array ( [id] => 9049191 [patent_doc_number] => 08543749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'System and method of increasing data processing on a diagnostic tool' [patent_app_type] => utility [patent_app_number] => 13/590932 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2926 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590932 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590932
System and method of increasing data processing on a diagnostic tool Aug 20, 2012 Issued
Array ( [id] => 9282841 [patent_doc_number] => 20140032809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'COMPOSITE DATA TRANSMISSION INTERFACE AND A JUDGMENT METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/590391 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590391
Composite data transmission interface and a judgment method thereof Aug 20, 2012 Issued
Array ( [id] => 9150435 [patent_doc_number] => 20130304958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'System and Method for Processing Device with Differentiated Execution Mode' [patent_app_type] => utility [patent_app_number] => 13/590017 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7535 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590017
System and method for processing device with differentiated execution mode Aug 19, 2012 Issued
Array ( [id] => 9171929 [patent_doc_number] => 20130313914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'CONTROL CIRCUIT FOR UNIVERSAL SERIAL BUS CONNECTOR' [patent_app_type] => utility [patent_app_number] => 13/589241 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 910 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/589241
CONTROL CIRCUIT FOR UNIVERSAL SERIAL BUS CONNECTOR Aug 19, 2012 Abandoned
Array ( [id] => 9320543 [patent_doc_number] => 20140052881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'SYSTEMS AND METHODS FOR CONCATENATING MULTIPLE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/589839 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/589839
Systems and methods for concatenating multiple devices Aug 19, 2012 Issued
Array ( [id] => 9320544 [patent_doc_number] => 20140052882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'Latency Sensitive Software Interrupt and Thread Scheduling' [patent_app_type] => utility [patent_app_number] => 13/587737 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587737 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/587737
Latency sensitive software interrupt and thread scheduling Aug 15, 2012 Issued
Array ( [id] => 9967757 [patent_doc_number] => 09015392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Multi-chip package and operating method thereof' [patent_app_type] => utility [patent_app_number] => 13/572086 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3028 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572086
Multi-chip package and operating method thereof Aug 9, 2012 Issued
Array ( [id] => 11680385 [patent_doc_number] => 09678917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Communications assembly having logic multichannel communication via a physical transmission path for serial interchip data transmission' [patent_app_type] => utility [patent_app_number] => 14/346943 [patent_app_country] => US [patent_app_date] => 2012-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3595 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14346943 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/346943
Communications assembly having logic multichannel communication via a physical transmission path for serial interchip data transmission Aug 5, 2012 Issued
Array ( [id] => 8703772 [patent_doc_number] => 08397007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Interrupt moderation' [patent_app_type] => utility [patent_app_number] => 13/549863 [patent_app_country] => US [patent_app_date] => 2012-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6569 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13549863 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/549863
Interrupt moderation Jul 15, 2012 Issued
Array ( [id] => 8485022 [patent_doc_number] => 20120284429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Dynamic Address Change for Slave Devices on a Shared Bus' [patent_app_type] => utility [patent_app_number] => 13/550579 [patent_app_country] => US [patent_app_date] => 2012-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6478 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13550579 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/550579
Dynamic address change for slave devices on a shared bus Jul 15, 2012 Issued
Array ( [id] => 9665754 [patent_doc_number] => 08812762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Presence detectable baffle for electrical components in a computing system' [patent_app_type] => utility [patent_app_number] => 13/534255 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8791 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534255
Presence detectable baffle for electrical components in a computing system Jun 26, 2012 Issued
Array ( [id] => 8463030 [patent_doc_number] => 20120268199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'Chip Having Register to Store Value that Represents Adjustment to Reference Voltage' [patent_app_type] => utility [patent_app_number] => 13/535228 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12968 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535228
Chip having register to store value that represents adjustment to reference voltage Jun 26, 2012 Issued
Array ( [id] => 9264727 [patent_doc_number] => 20130346656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Providing A Serial Protocol For A Bidirectional Serial Interconnect' [patent_app_type] => utility [patent_app_number] => 13/532962 [patent_app_country] => US [patent_app_date] => 2012-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13532962 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/532962
Providing a serial protocol for a bidirectional serial interconnect Jun 25, 2012 Issued
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