
Glenn Allen Auve
Examiner (ID: 8999)
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2111, 2186, 2308, 2781, 2305, 2175, 2181, 2185 |
| Total Applications | 2279 |
| Issued Applications | 2039 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8626986
[patent_doc_number] => 08359490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-22
[patent_title] => 'Memory controller, system including the controller, and memory delay amount control method'
[patent_app_type] => utility
[patent_app_number] => 13/462689
[patent_app_country] => US
[patent_app_date] => 2012-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2825
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462689
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/462689 | Memory controller, system including the controller, and memory delay amount control method | May 1, 2012 | Issued |
Array
(
[id] => 9282843
[patent_doc_number] => 20140032811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'MULTI-ROOT PERIPHERAL CONNECT INTERFACE MANAGER'
[patent_app_type] => utility
[patent_app_number] => 14/112379
[patent_app_country] => US
[patent_app_date] => 2012-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6592
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14112379
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/112379 | Multi-root peripheral component interconnect manager | Apr 19, 2012 | Issued |
Array
(
[id] => 8667430
[patent_doc_number] => 08380903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-19
[patent_title] => 'Administering the polling of a number of devices for device status'
[patent_app_type] => utility
[patent_app_number] => 13/442000
[patent_app_country] => US
[patent_app_date] => 2012-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6121
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442000
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/442000 | Administering the polling of a number of devices for device status | Apr 8, 2012 | Issued |
Array
(
[id] => 9878855
[patent_doc_number] => 08966151
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal'
[patent_app_type] => utility
[patent_app_number] => 13/435445
[patent_app_country] => US
[patent_app_date] => 2012-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7927
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435445
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/435445 | Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal | Mar 29, 2012 | Issued |
Array
(
[id] => 9341345
[patent_doc_number] => 20140068129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-06
[patent_title] => 'METHOD FOR IMPLEMENTING SECURE DATA CHANNEL BETWEEN PROCESSOR AND DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/997956
[patent_app_country] => US
[patent_app_date] => 2012-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4836
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997956
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/997956 | Method for implementing secure data channel between processor and devices | Mar 27, 2012 | Issued |
Array
(
[id] => 8558075
[patent_doc_number] => 08332559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-11
[patent_title] => 'Power managed lock optimization'
[patent_app_type] => utility
[patent_app_number] => 13/413796
[patent_app_country] => US
[patent_app_date] => 2012-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 7587
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413796
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/413796 | Power managed lock optimization | Mar 6, 2012 | Issued |
Array
(
[id] => 8291519
[patent_doc_number] => 20120179849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-12
[patent_title] => 'PROGRAMMABLE CONTROLLER'
[patent_app_type] => utility
[patent_app_number] => 13/399100
[patent_app_country] => US
[patent_app_date] => 2012-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8335
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13399100
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/399100 | Programmable controller using master-slave communication | Feb 16, 2012 | Issued |
Array
(
[id] => 10854213
[patent_doc_number] => 08880924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-04
[patent_title] => 'Hot-plugging of multi-core processor'
[patent_app_type] => utility
[patent_app_number] => 13/396617
[patent_app_country] => US
[patent_app_date] => 2012-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7529
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396617
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/396617 | Hot-plugging of multi-core processor | Feb 14, 2012 | Issued |
Array
(
[id] => 9555539
[patent_doc_number] => 08762611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'System comprising a bus, and method to transmit data over a bus system'
[patent_app_type] => utility
[patent_app_number] => 13/397229
[patent_app_country] => US
[patent_app_date] => 2012-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6072
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397229
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/397229 | System comprising a bus, and method to transmit data over a bus system | Feb 14, 2012 | Issued |
Array
(
[id] => 8360800
[patent_doc_number] => 20120215955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-23
[patent_title] => 'System on Chip Comprising Interconnector and Control Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 13/396155
[patent_app_country] => US
[patent_app_date] => 2012-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5096
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396155
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/396155 | System on chip comprising interconnector and control method thereof | Feb 13, 2012 | Issued |
Array
(
[id] => 9493055
[patent_doc_number] => 20140143461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-22
[patent_title] => 'SERIAL INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 13/985715
[patent_app_country] => US
[patent_app_date] => 2012-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5082
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985715
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/985715 | Synchronous serial data-exchange system | Feb 13, 2012 | Issued |
Array
(
[id] => 9444101
[patent_doc_number] => 08713232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-29
[patent_title] => 'Apparatus and method for transferring a data signal propagated along a bidirectional communication path within a data processing apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/368385
[patent_app_country] => US
[patent_app_date] => 2012-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 8702
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 389
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368385
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/368385 | Apparatus and method for transferring a data signal propagated along a bidirectional communication path within a data processing apparatus | Feb 7, 2012 | Issued |
Array
(
[id] => 9680398
[patent_doc_number] => 08819325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Interface device and system including the same'
[patent_app_type] => utility
[patent_app_number] => 13/368353
[patent_app_country] => US
[patent_app_date] => 2012-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7324
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368353
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/368353 | Interface device and system including the same | Feb 7, 2012 | Issued |
Array
(
[id] => 8372373
[patent_doc_number] => 20120221763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'GATEWAY APPARATUS FOR SUBSTATION AUTOMATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/369250
[patent_app_country] => US
[patent_app_date] => 2012-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4764
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369250
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/369250 | Gateway apparatus for substation automation system | Feb 7, 2012 | Issued |
Array
(
[id] => 9592756
[patent_doc_number] => 08782321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-15
[patent_title] => 'PCI express tunneling over a multi-protocol I/O interconnect'
[patent_app_type] => utility
[patent_app_number] => 13/369140
[patent_app_country] => US
[patent_app_date] => 2012-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 26
[patent_no_of_words] => 11175
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369140
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/369140 | PCI express tunneling over a multi-protocol I/O interconnect | Feb 7, 2012 | Issued |
Array
(
[id] => 9585700
[patent_doc_number] => 08775710
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-08
[patent_title] => 'Mobile information handling apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/368153
[patent_app_country] => US
[patent_app_date] => 2012-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 6040
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368153
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/368153 | Mobile information handling apparatus | Feb 6, 2012 | Issued |
Array
(
[id] => 8959065
[patent_doc_number] => 08504859
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-06
[patent_title] => 'Data interface power consumption control'
[patent_app_type] => utility
[patent_app_number] => 13/363129
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6740
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363129
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363129 | Data interface power consumption control | Jan 30, 2012 | Issued |
Array
(
[id] => 11258526
[patent_doc_number] => 09483426
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-01
[patent_title] => 'Locking a system management interrupt (SMI) enable register of a chipset'
[patent_app_type] => utility
[patent_app_number] => 14/364706
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7315
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364706
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/364706 | Locking a system management interrupt (SMI) enable register of a chipset | Jan 30, 2012 | Issued |
Array
(
[id] => 11769499
[patent_doc_number] => 09378164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-28
[patent_title] => 'Interrupt return instruction with embedded interrupt service functionality'
[patent_app_type] => utility
[patent_app_number] => 13/997651
[patent_app_country] => US
[patent_app_date] => 2011-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3988
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997651
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/997651 | Interrupt return instruction with embedded interrupt service functionality | Dec 21, 2011 | Issued |
Array
(
[id] => 8687638
[patent_doc_number] => RE044051
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2013-03-05
[patent_title] => 'Data bus line control circuit'
[patent_app_type] => reissue
[patent_app_number] => 13/335207
[patent_app_country] => US
[patent_app_date] => 2011-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2327
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335207
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/335207 | Data bus line control circuit | Dec 21, 2011 | Issued |