Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10616685 [patent_doc_number] => 09336130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Methods, systems, and computer readable media for providing basic input/output system (BIOS) data and non-BIOS data on the same non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/308117 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4481 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308117 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308117
Methods, systems, and computer readable media for providing basic input/output system (BIOS) data and non-BIOS data on the same non-volatile memory Nov 29, 2011 Issued
Array ( [id] => 8574662 [patent_doc_number] => 08341323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method and apparatus for data movement in a system on a chip' [patent_app_type] => utility [patent_app_number] => 13/302854 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2582 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302854
Method and apparatus for data movement in a system on a chip Nov 21, 2011 Issued
Array ( [id] => 8971755 [patent_doc_number] => 08510584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Ultra low power sleep mode' [patent_app_type] => utility [patent_app_number] => 13/296977 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296977
Ultra low power sleep mode Nov 14, 2011 Issued
Array ( [id] => 10651247 [patent_doc_number] => 09367500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone' [patent_app_type] => utility [patent_app_number] => 13/997623 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997623
Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone Nov 8, 2011 Issued
Array ( [id] => 11775223 [patent_doc_number] => 09384154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Method to emulate message signaled interrupts with multiple interrupt vectors' [patent_app_type] => utility [patent_app_number] => 13/976195 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976195
Method to emulate message signaled interrupts with multiple interrupt vectors Nov 2, 2011 Issued
Array ( [id] => 9571469 [patent_doc_number] => 20140189182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD TO ACCELERATE MESSAGE SIGNALED INTERRUPT PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/976213 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976213 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976213
Method to accelerate message signaled interrupt processing Nov 2, 2011 Issued
Array ( [id] => 7780549 [patent_doc_number] => 20120042105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'BUS ARBITRATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/279974 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5511 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042105.pdf [firstpage_image] =>[orig_patent_app_number] => 13279974 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/279974
BUS ARBITRATION APPARATUS Oct 23, 2011 Abandoned
Array ( [id] => 9444205 [patent_doc_number] => 08713340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method and apparatus for power management control of an embedded memory having sleep and shutdown features' [patent_app_type] => utility [patent_app_number] => 13/271640 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 12258 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271640 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271640
Method and apparatus for power management control of an embedded memory having sleep and shutdown features Oct 11, 2011 Issued
Array ( [id] => 8143479 [patent_doc_number] => 20120096287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'COORDINATED APPROACH BETWEEN MIDDLEWARE APPLICATION AND SUB-SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/271490 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3243 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096287.pdf [firstpage_image] =>[orig_patent_app_number] => 13271490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271490
Coordinated approach between middleware application and sub-systems Oct 11, 2011 Issued
Array ( [id] => 8143503 [patent_doc_number] => 20120096299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'UNIVERSAL SERIAL BUS DONGLE AND METHOD OF CONTROLLING POWER THEREOF' [patent_app_type] => utility [patent_app_number] => 13/271623 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3391 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096299.pdf [firstpage_image] =>[orig_patent_app_number] => 13271623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271623
UNIVERSAL SERIAL BUS DONGLE AND METHOD OF CONTROLLING POWER THEREOF Oct 11, 2011 Abandoned
Array ( [id] => 8769407 [patent_doc_number] => 20130097444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'USING LATCHED EVENTS TO MANAGE SLEEP/WAKE SEQUENCES ON COMPUTER SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/271409 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5425 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271409
Using latched events to manage sleep/wake sequences on computer systems Oct 11, 2011 Issued
Array ( [id] => 8757070 [patent_doc_number] => 20130091375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'Advanced Array Local Clock Buffer Base Block Circuit' [patent_app_type] => utility [patent_app_number] => 13/269654 [patent_app_country] => US [patent_app_date] => 2011-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4867 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269654 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/269654
Advanced Array Local Clock Buffer Base Block Circuit Oct 9, 2011 Abandoned
Array ( [id] => 8280031 [patent_doc_number] => 20120173911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'METHOD AND SYSTEM FOR DETECTING WHETHER A COMPUTER SERVER HAS SHUT DOWN GRACEFULLY' [patent_app_type] => utility [patent_app_number] => 13/269867 [patent_app_country] => US [patent_app_date] => 2011-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3173 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269867 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/269867
Method and system for detecting whether a computer server has shut down gracefully Oct 9, 2011 Issued
Array ( [id] => 8722659 [patent_doc_number] => 20130073876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'NETWORK WAKE UP SYSTEM WITH PROTECTION FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/267856 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 885 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267856 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267856
Network wake up system with protection function Oct 5, 2011 Issued
Array ( [id] => 7739217 [patent_doc_number] => 20120019069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'COMPUTER SYSTEM AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/250033 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5974 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20120019069.pdf [firstpage_image] =>[orig_patent_app_number] => 13250033 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250033
Computer system for supplying electric power to external apparatus and control method thereof Sep 29, 2011 Issued
Array ( [id] => 8058839 [patent_doc_number] => 20120079147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'BUS CONTROL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/247163 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14190 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079147.pdf [firstpage_image] =>[orig_patent_app_number] => 13247163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247163
Bus controller arranged between a bus master and a networked communication bus in order to control the transmission route of a packet that flows through the communication bus, and simulation program to design such a bus controller Sep 27, 2011 Issued
Array ( [id] => 10171103 [patent_doc_number] => 09201812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Multiple logical representations of audio functions in a wireless audio transmitter that transmits audio data at different data rates' [patent_app_type] => utility [patent_app_number] => 13/247975 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6499 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247975
Multiple logical representations of audio functions in a wireless audio transmitter that transmits audio data at different data rates Sep 27, 2011 Issued
Array ( [id] => 9102607 [patent_doc_number] => 08566501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Circuit for simultaneously analyzing performance and bugs and method thereof' [patent_app_type] => utility [patent_app_number] => 13/233008 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1800 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13233008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/233008
Circuit for simultaneously analyzing performance and bugs and method thereof Sep 13, 2011 Issued
Array ( [id] => 9458452 [patent_doc_number] => 08719476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Communication system, master device and slave device, and communication method, configured to handle plural concurrent requests' [patent_app_type] => utility [patent_app_number] => 13/231128 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6515 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231128 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231128
Communication system, master device and slave device, and communication method, configured to handle plural concurrent requests Sep 12, 2011 Issued
Array ( [id] => 8709845 [patent_doc_number] => 20130067134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'PSEUDO MULTI-MASTER I2C OPERATION IN A BLADE SERVER CHASSIS' [patent_app_type] => utility [patent_app_number] => 13/231040 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5852 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231040 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231040
Pseudo multi-master I2C operation in a blade server chassis Sep 12, 2011 Issued
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