
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9077376
[patent_doc_number] => 08554969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-08
[patent_title] => 'Electronic device with expansion card'
[patent_app_type] => utility
[patent_app_number] => 13/228450
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228450 | Electronic device with expansion card | Sep 8, 2011 | Issued |
Array
(
[id] => 8698975
[patent_doc_number] => 20130060984
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[patent_kind] => A1
[patent_issue_date] => 2013-03-07
[patent_title] => 'Administering Computing System Resources In A Computing System'
[patent_app_type] => utility
[patent_app_number] => 13/226134
[patent_app_country] => US
[patent_app_date] => 2011-09-06
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[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/226134 | Administering computing system resources in a computing system | Sep 5, 2011 | Issued |
Array
(
[id] => 9752196
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[patent_kind] => B2
[patent_issue_date] => 2014-09-23
[patent_title] => 'Presence detectable baffle for electrical components in a computing system'
[patent_app_type] => utility
[patent_app_number] => 13/226035
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[patent_app_date] => 2011-09-06
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[patent_drawing_sheets_cnt] => 6
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Array
(
[id] => 7671387
[patent_doc_number] => 20110320656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-29
[patent_title] => 'Techniques for obtaining a serial number for a storage device'
[patent_app_type] => utility
[patent_app_number] => 13/225519
[patent_app_country] => US
[patent_app_date] => 2011-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/225519 | Techniques for obtaining a serial number for a storage device | Sep 4, 2011 | Abandoned |
Array
(
[id] => 9257691
[patent_doc_number] => 08621131
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[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'Uniform multi-chip identification and routing system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/221465 | Uniform multi-chip identification and routing system | Aug 29, 2011 | Issued |
Array
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[patent_issue_date] => 2014-11-04
[patent_title] => 'Pessimistic interrupt affinity for devices'
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Array
(
[id] => 9257676
[patent_doc_number] => 08621116
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[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'Dynamic address change optimizations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/218658 | Dynamic address change optimizations | Aug 25, 2011 | Issued |
Array
(
[id] => 7658372
[patent_doc_number] => 20110307641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-15
[patent_title] => 'Lazy Handling of End of Interrupt Messages in a Virtualized Environment'
[patent_app_type] => utility
[patent_app_number] => 13/216584
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[patent_app_date] => 2011-08-24
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[pdf_file] => publications/A1/0307/20110307641.pdf
[firstpage_image] =>[orig_patent_app_number] => 13216584
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/216584 | Lazy handling of end of interrupt messages in a virtualized environment | Aug 23, 2011 | Issued |
Array
(
[id] => 8213801
[patent_doc_number] => 20120131255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'MULTI-PORT SYSTEM AND METHOD FOR ROUTING A DATA ELEMENT WITHIN AN INTERCONNECTION FABRIC'
[patent_app_type] => utility
[patent_app_number] => 13/215011
[patent_app_country] => US
[patent_app_date] => 2011-08-22
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[pdf_file] => publications/A1/0131/20120131255.pdf
[firstpage_image] =>[orig_patent_app_number] => 13215011
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/215011 | Multi-port system and method for routing a data element within an interconnection fabric | Aug 21, 2011 | Issued |
Array
(
[id] => 9242180
[patent_doc_number] => 08606985
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[patent_issue_date] => 2013-12-10
[patent_title] => 'Controlled device to control switching between transmission paths for transmitting data at different rate'
[patent_app_type] => utility
[patent_app_number] => 13/198329
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[patent_app_date] => 2011-08-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/198329 | Controlled device to control switching between transmission paths for transmitting data at different rate | Aug 3, 2011 | Issued |
Array
(
[id] => 8985037
[patent_doc_number] => 08516167
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[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Microcontroller system bus scheduling for multiport slave modules'
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[patent_app_date] => 2011-08-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/197547 | Microcontroller system bus scheduling for multiport slave modules | Aug 2, 2011 | Issued |
Array
(
[id] => 8193875
[patent_doc_number] => 20120119854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'SEGMENTED TRANSMISSION SIGNAL CIRCUIT'
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Array
(
[id] => 7569182
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[patent_title] => 'Memory Controller and Method Utilizing Equalization Co-Efficient Setting'
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Array
(
[id] => 7770298
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[patent_issue_date] => 2012-02-09
[patent_title] => 'SWITCHING CIRCUIT, INFORMATION PROCESSING APPARATUS, AND SWITCHING CIRCUIT CONTROL METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/195345 | Switching circuit connected to an I/O device, and switching circuit connected to an I/O device control method | Jul 31, 2011 | Issued |
| 13/195357 | Apparatus For Providing I/O Support To A Computer System And Method Of Use Thereof | Jul 31, 2011 | Abandoned |
Array
(
[id] => 9012368
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[patent_title] => 'Main board and method for dynamically configuring periperhal component interconnect express ports thereof'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/192006 | Configurable patient monitoring system | Jul 26, 2011 | Issued |
Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/191892 | PCI-E system having reconfigurable link architecture | Jul 26, 2011 | Issued |