
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6232963
[patent_doc_number] => 20100265537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCI-E) SIGNAL TRANSMISSION APPARATUS AND IMAGE FORMING APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/700846
[patent_app_country] => US
[patent_app_date] => 2010-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4343
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0265/20100265537.pdf
[firstpage_image] =>[orig_patent_app_number] => 12700846
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/700846 | Peripheral component interconnect express (PCI-E) signal transmission apparatus and image forming apparatus using the same | Feb 4, 2010 | Issued |
Array
(
[id] => 9714268
[patent_doc_number] => 08838867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Software-based virtual PCI system'
[patent_app_type] => utility
[patent_app_number] => 12/655135
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3978
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12655135
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/655135 | Software-based virtual PCI system | Dec 22, 2009 | Issued |
Array
(
[id] => 9392265
[patent_doc_number] => 08688887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-01
[patent_title] => 'Computer peripheral expansion apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/644629
[patent_app_country] => US
[patent_app_date] => 2009-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5078
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644629
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/644629 | Computer peripheral expansion apparatus | Dec 21, 2009 | Issued |
Array
(
[id] => 6446750
[patent_doc_number] => 20100169695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'AUTONOMOUS MULTI-DEVICE EVENT SYNCHRONIZATION AND SEQUENCING TECHNIQUE ELIMINATING MASTER AND SLAVE ASSIGNMENTS'
[patent_app_type] => utility
[patent_app_number] => 12/645258
[patent_app_country] => US
[patent_app_date] => 2009-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7644
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20100169695.pdf
[firstpage_image] =>[orig_patent_app_number] => 12645258
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/645258 | Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments | Dec 21, 2009 | Issued |
Array
(
[id] => 6443523
[patent_doc_number] => 20100169533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'MULTI-PORT SYSTEM AND METHOD FOR ROUTING A DATA ELEMENT WITHIN AN INTERCONNECTION FABRIC'
[patent_app_type] => utility
[patent_app_number] => 12/643385
[patent_app_country] => US
[patent_app_date] => 2009-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11053
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20100169533.pdf
[firstpage_image] =>[orig_patent_app_number] => 12643385
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/643385 | Multi-port system and method for routing a data element within an interconnection fabric | Dec 20, 2009 | Issued |
Array
(
[id] => 10021570
[patent_doc_number] => 09064058
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Virtualized PCI endpoint for extended systems'
[patent_app_type] => utility
[patent_app_number] => 12/653785
[patent_app_country] => US
[patent_app_date] => 2009-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4579
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12653785
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/653785 | Virtualized PCI endpoint for extended systems | Dec 17, 2009 | Issued |
Array
(
[id] => 6387365
[patent_doc_number] => 20100082863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES'
[patent_app_type] => utility
[patent_app_number] => 12/630139
[patent_app_country] => US
[patent_app_date] => 2009-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8672
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20100082863.pdf
[firstpage_image] =>[orig_patent_app_number] => 12630139
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/630139 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Dec 2, 2009 | Issued |
Array
(
[id] => 8472623
[patent_doc_number] => 08301816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-30
[patent_title] => 'Memory access controller, system, and method'
[patent_app_type] => utility
[patent_app_number] => 12/628633
[patent_app_country] => US
[patent_app_date] => 2009-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6668
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12628633
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/628633 | Memory access controller, system, and method | Nov 30, 2009 | Issued |
Array
(
[id] => 5990422
[patent_doc_number] => 20110099313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-28
[patent_title] => 'SYSTEM AND METHOD FOR CONTROLLING INTERRUPTION OF A PROCESS IN ELECTRONIC EQUIPMENT BASED ON PRIORITY OF THE PROCESS, AND PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/626264
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5712
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20110099313.pdf
[firstpage_image] =>[orig_patent_app_number] => 12626264
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/626264 | System and method for controlling interruption of a process in electronic equipment based on priority of the process, and program | Nov 24, 2009 | Issued |
Array
(
[id] => 8626916
[patent_doc_number] => 08359419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-22
[patent_title] => 'System LSI having plural buses'
[patent_app_type] => utility
[patent_app_number] => 12/617291
[patent_app_country] => US
[patent_app_date] => 2009-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 13686
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 369
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12617291
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/617291 | System LSI having plural buses | Nov 11, 2009 | Issued |
Array
(
[id] => 5956663
[patent_doc_number] => 20110035520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'MOTHERBOARD FOR SELECTING ONE OF SUB-SYSTEMS IMMEDIATELY'
[patent_app_type] => utility
[patent_app_number] => 12/611410
[patent_app_country] => US
[patent_app_date] => 2009-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5840
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20110035520.pdf
[firstpage_image] =>[orig_patent_app_number] => 12611410
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/611410 | Motherboard with selected sub-system controlling shared peripherals | Nov 2, 2009 | Issued |
Array
(
[id] => 6040588
[patent_doc_number] => 20110093637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-21
[patent_title] => 'Interrupt Moderation'
[patent_app_type] => utility
[patent_app_number] => 12/580913
[patent_app_country] => US
[patent_app_date] => 2009-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6496
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20110093637.pdf
[firstpage_image] =>[orig_patent_app_number] => 12580913
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/580913 | Interrupt moderation | Oct 15, 2009 | Issued |
Array
(
[id] => 7679706
[patent_doc_number] => 20100106881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'HOT PLUG AD HOC COMPUTER RESOURCE ALLOCATION'
[patent_app_type] => utility
[patent_app_number] => 12/587779
[patent_app_country] => US
[patent_app_date] => 2009-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2753
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20100106881.pdf
[firstpage_image] =>[orig_patent_app_number] => 12587779
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/587779 | Hot plug ad hoc computer resource allocation | Oct 12, 2009 | Issued |
Array
(
[id] => 6125178
[patent_doc_number] => 20110078352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'Administering The Polling Of A Number Of Devices For Device Status'
[patent_app_type] => utility
[patent_app_number] => 12/570881
[patent_app_country] => US
[patent_app_date] => 2009-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6091
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20110078352.pdf
[firstpage_image] =>[orig_patent_app_number] => 12570881
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/570881 | Administering the polling of a number of devices for device status | Sep 29, 2009 | Issued |
Array
(
[id] => 48618
[patent_doc_number] => 07779190
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Arbitration device for arbitrating among a plurality of master devices, arbitration method, and video processing device including the arbitration device'
[patent_app_type] => utility
[patent_app_number] => 12/559916
[patent_app_country] => US
[patent_app_date] => 2009-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8473
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/779/07779190.pdf
[firstpage_image] =>[orig_patent_app_number] => 12559916
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/559916 | Arbitration device for arbitrating among a plurality of master devices, arbitration method, and video processing device including the arbitration device | Sep 14, 2009 | Issued |
Array
(
[id] => 8354928
[patent_doc_number] => 08250273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-21
[patent_title] => 'Secure handling and routing of message-signaled interrupts'
[patent_app_type] => utility
[patent_app_number] => 12/559002
[patent_app_country] => US
[patent_app_date] => 2009-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4375
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12559002
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/559002 | Secure handling and routing of message-signaled interrupts | Sep 13, 2009 | Issued |
Array
(
[id] => 6491417
[patent_doc_number] => 20100042810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-18
[patent_title] => 'MULTIPROCESSOR METHOD AND SYSTEM USING STACKED PROCESSOR MODULES AND BOARD-TO-BOARD CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 12/558255
[patent_app_country] => US
[patent_app_date] => 2009-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5225
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20100042810.pdf
[firstpage_image] =>[orig_patent_app_number] => 12558255
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/558255 | Multiprocessor method and system using stacked processor modules and board-to-board connectors | Sep 10, 2009 | Issued |
Array
(
[id] => 4447348
[patent_doc_number] => 07930464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Scalable memory and I/O multiprocessor systems'
[patent_app_type] => utility
[patent_app_number] => 12/549491
[patent_app_country] => US
[patent_app_date] => 2009-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4741
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/930/07930464.pdf
[firstpage_image] =>[orig_patent_app_number] => 12549491
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/549491 | Scalable memory and I/O multiprocessor systems | Aug 27, 2009 | Issued |
Array
(
[id] => 6227436
[patent_doc_number] => 20100057975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/545312
[patent_app_country] => US
[patent_app_date] => 2009-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6109
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20100057975.pdf
[firstpage_image] =>[orig_patent_app_number] => 12545312
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/545312 | Storage device having a plurality of interfaces for connection to an external device | Aug 20, 2009 | Issued |
Array
(
[id] => 6616212
[patent_doc_number] => 20100049892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'METHOD OF ROUTING AN INTERRUPT SIGNAL DIRECTLY TO A VIRTUAL PROCESSING UNIT IN A SYSTEM WITH ONE OR MORE PHYSICAL PROCESSING UNITS'
[patent_app_type] => utility
[patent_app_number] => 12/541792
[patent_app_country] => US
[patent_app_date] => 2009-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4459
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20100049892.pdf
[firstpage_image] =>[orig_patent_app_number] => 12541792
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/541792 | Method of routing an interrupt signal directly to a virtual processing unit in a system with one or more physical processing units | Aug 13, 2009 | Issued |