
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6387379
[patent_doc_number] => 20100082866
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[patent_title] => 'Providing a set aside mechanism for posted interrupt transactions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/286324 | Providing a set aside mechanism for posted interrupt transactions | Sep 29, 2008 | Issued |
Array
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Array
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[patent_title] => 'MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS'
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Array
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[patent_issue_date] => 2011-03-03
[patent_title] => 'Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip'
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Array
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[patent_title] => 'Method and apparatus for wireless digital content management'
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Array
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[patent_title] => 'Multi-Mode Bus Inversion Method and Apparatus'
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Array
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[patent_title] => 'PCI Express Switch with Backwards Compatibility'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195122 | PCI express switch with backwards compatibility | Aug 19, 2008 | Issued |
Array
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[patent_title] => 'Management of power domains in an integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/192683 | Management of power domains in an integrated circuit | Aug 14, 2008 | Issued |
Array
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[id] => 6218155
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[patent_title] => 'Dynamic Utilization of Power-Down Modes in Multi-Core Memory Modules'
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Array
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[patent_title] => 'Platform-Based Idle-Time Processing'
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Array
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[patent_title] => 'Detecting circuit for IEEE 1394 device'
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Array
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[patent_title] => 'SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA'
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Array
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Array
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Array
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Array
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