Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6387379 [patent_doc_number] => 20100082866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Providing a set aside mechanism for posted interrupt transactions' [patent_app_type] => utility [patent_app_number] => 12/286324 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082866.pdf [firstpage_image] =>[orig_patent_app_number] => 12286324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/286324
Providing a set aside mechanism for posted interrupt transactions Sep 29, 2008 Issued
Array ( [id] => 28107 [patent_doc_number] => 07797476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Flexible connection scheme between multiple masters and slaves' [patent_app_type] => utility [patent_app_number] => 12/233910 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2286 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797476.pdf [firstpage_image] =>[orig_patent_app_number] => 12233910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233910
Flexible connection scheme between multiple masters and slaves Sep 18, 2008 Issued
Array ( [id] => 6619259 [patent_doc_number] => 20100064080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/208640 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1132 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064080.pdf [firstpage_image] =>[orig_patent_app_number] => 12208640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/208640
MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS Sep 10, 2008 Abandoned
Array ( [id] => 6031277 [patent_doc_number] => 20110055449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip' [patent_app_type] => utility [patent_app_number] => 12/677913 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 35787 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055449.pdf [firstpage_image] =>[orig_patent_app_number] => 12677913 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/677913
Logic chip, method and computer program for providing a configuration information for a configurable logic chip Sep 7, 2008 Issued
Array ( [id] => 8958978 [patent_doc_number] => 08504772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and apparatus for wireless digital content management' [patent_app_type] => utility [patent_app_number] => 12/863556 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3344 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12863556 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/863556
Method and apparatus for wireless digital content management Sep 3, 2008 Issued
Array ( [id] => 6227431 [patent_doc_number] => 20100057971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'Multi-Mode Bus Inversion Method and Apparatus' [patent_app_type] => utility [patent_app_number] => 12/202485 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3382 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20100057971.pdf [firstpage_image] =>[orig_patent_app_number] => 12202485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202485
Multi-mode bus inversion method and apparatus Sep 1, 2008 Issued
Array ( [id] => 4948378 [patent_doc_number] => 20080304504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'PCI Express Switch with Backwards Compatibility' [patent_app_type] => utility [patent_app_number] => 12/195122 [patent_app_country] => US [patent_app_date] => 2008-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20080304504.pdf [firstpage_image] =>[orig_patent_app_number] => 12195122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/195122
PCI express switch with backwards compatibility Aug 19, 2008 Issued
Array ( [id] => 4641982 [patent_doc_number] => 08020017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Management of power domains in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/192683 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4458 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020017.pdf [firstpage_image] =>[orig_patent_app_number] => 12192683 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192683
Management of power domains in an integrated circuit Aug 14, 2008 Issued
Array ( [id] => 6218155 [patent_doc_number] => 20110138387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Dynamic Utilization of Power-Down Modes in Multi-Core Memory Modules' [patent_app_type] => utility [patent_app_number] => 13/058067 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8056 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138387.pdf [firstpage_image] =>[orig_patent_app_number] => 13058067 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/058067
Dynamic utilization of power-down modes in multi-core memory modules Aug 12, 2008 Issued
Array ( [id] => 6262900 [patent_doc_number] => 20100031071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Platform-Based Idle-Time Processing' [patent_app_type] => utility [patent_app_number] => 12/182074 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031071.pdf [firstpage_image] =>[orig_patent_app_number] => 12182074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182074
Platform-based idle-time processing Jul 28, 2008 Issued
Array ( [id] => 66371 [patent_doc_number] => 07765355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Detecting circuit for IEEE 1394 device' [patent_app_type] => utility [patent_app_number] => 12/178657 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 646 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765355.pdf [firstpage_image] =>[orig_patent_app_number] => 12178657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/178657
Detecting circuit for IEEE 1394 device Jul 23, 2008 Issued
Array ( [id] => 4961605 [patent_doc_number] => 20080276030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA' [patent_app_type] => utility [patent_app_number] => 12/178288 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5676 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276030.pdf [firstpage_image] =>[orig_patent_app_number] => 12178288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/178288
SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA Jul 22, 2008 Abandoned
Array ( [id] => 8958954 [patent_doc_number] => 08504749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Synchronization of multiple processor cores' [patent_app_type] => utility [patent_app_number] => 13/055347 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5471 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13055347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/055347
Synchronization of multiple processor cores Jul 21, 2008 Issued
Array ( [id] => 4530236 [patent_doc_number] => 07913025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-22 [patent_title] => 'Method and system for a storage device' [patent_app_type] => utility [patent_app_number] => 12/175496 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913025.pdf [firstpage_image] =>[orig_patent_app_number] => 12175496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/175496
Method and system for a storage device Jul 17, 2008 Issued
Array ( [id] => 4521994 [patent_doc_number] => 07917683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Method and system for utilizing multiple storage devices' [patent_app_type] => utility [patent_app_number] => 12/175490 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7235 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917683.pdf [firstpage_image] =>[orig_patent_app_number] => 12175490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/175490
Method and system for utilizing multiple storage devices Jul 17, 2008 Issued
Array ( [id] => 7495043 [patent_doc_number] => 08032680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Lazy handling of end of interrupt messages in a virtualized environment' [patent_app_type] => utility [patent_app_number] => 12/163891 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032680.pdf [firstpage_image] =>[orig_patent_app_number] => 12163891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163891
Lazy handling of end of interrupt messages in a virtualized environment Jun 26, 2008 Issued
Array ( [id] => 7547848 [patent_doc_number] => 08055829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Adaptable hardware-programmable transmission interface for industrial PCS' [patent_app_type] => utility [patent_app_number] => 12/146103 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1367 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055829.pdf [firstpage_image] =>[orig_patent_app_number] => 12146103 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146103
Adaptable hardware-programmable transmission interface for industrial PCS Jun 24, 2008 Issued
Array ( [id] => 48622 [patent_doc_number] => 07779194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Data modification module' [patent_app_type] => utility [patent_app_number] => 12/144739 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779194.pdf [firstpage_image] =>[orig_patent_app_number] => 12144739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144739
Data modification module Jun 23, 2008 Issued
Array ( [id] => 5311396 [patent_doc_number] => 20090018677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'UPNP CONTROL POINT AND METHOD OF HANDLING UPNP CONTROL REQUEST' [patent_app_type] => utility [patent_app_number] => 12/143900 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3954 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20090018677.pdf [firstpage_image] =>[orig_patent_app_number] => 12143900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143900
UPNP control point and method of handling UPNP control request Jun 22, 2008 Issued
Array ( [id] => 76322 [patent_doc_number] => 07757027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Control of master/slave communication within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/213470 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757027.pdf [firstpage_image] =>[orig_patent_app_number] => 12213470 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213470
Control of master/slave communication within an integrated circuit Jun 18, 2008 Issued
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