Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6741622 [patent_doc_number] => 20030158991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Transceiver circuitry for sending and detecting OOB signals on serial ATA buses' [patent_app_type] => new [patent_app_number] => 10/061631 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7285 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20030158991.pdf [firstpage_image] =>[orig_patent_app_number] => 10061631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061631
Transceiver circuitry for sending and detecting OOB signals on serial ATA buses Jan 31, 2002 Abandoned
Array ( [id] => 5847074 [patent_doc_number] => 20020133239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Device for connecting an industrial control unit to an industrial control panel' [patent_app_type] => new [patent_app_number] => 10/055989 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1789 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133239.pdf [firstpage_image] =>[orig_patent_app_number] => 10055989 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055989
Device for connecting an industrial control unit to an industrial control panel Jan 27, 2002 Abandoned
Array ( [id] => 5990633 [patent_doc_number] => 20020099896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Integrated circuit device having double data rate capability' [patent_app_type] => new [patent_app_number] => 10/054196 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15167 [patent_no_of_claims] => 150 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099896.pdf [firstpage_image] =>[orig_patent_app_number] => 10054196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054196
Integrated circuit device having double data rate capability Jan 21, 2002 Issued
Array ( [id] => 6661031 [patent_doc_number] => 20030135675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Configurable synchronous or asynchronous bus interface' [patent_app_type] => new [patent_app_number] => 10/052276 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4579 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135675.pdf [firstpage_image] =>[orig_patent_app_number] => 10052276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052276
Configurable synchronous or asynchronous bus interface Jan 16, 2002 Abandoned
Array ( [id] => 626305 [patent_doc_number] => 07139856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Use of set-by-read and set-by-write registers as semaphores' [patent_app_type] => utility [patent_app_number] => 10/037670 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6176 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139856.pdf [firstpage_image] =>[orig_patent_app_number] => 10037670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037670
Use of set-by-read and set-by-write registers as semaphores Jan 2, 2002 Issued
Array ( [id] => 984589 [patent_doc_number] => 06928504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'PC card motion detector' [patent_app_type] => utility [patent_app_number] => 10/040131 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928504.pdf [firstpage_image] =>[orig_patent_app_number] => 10040131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040131
PC card motion detector Jan 1, 2002 Issued
Array ( [id] => 6762980 [patent_doc_number] => 20030126342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'System to optimally order cycles originating from a single physical link' [patent_app_type] => new [patent_app_number] => 10/038844 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4891 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126342.pdf [firstpage_image] =>[orig_patent_app_number] => 10038844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038844
System to optimally order cycles originating from a single physical link Dec 30, 2001 Issued
Array ( [id] => 6648055 [patent_doc_number] => 20020087767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Apparatus and method of preventing congestion in message transmission system' [patent_app_type] => new [patent_app_number] => 10/026776 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2558 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087767.pdf [firstpage_image] =>[orig_patent_app_number] => 10026776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026776
Apparatus and method of preventing congestion in message transmission system Dec 26, 2001 Issued
Array ( [id] => 5971388 [patent_doc_number] => 20020091890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Synchronous memory device having automatic precharge' [patent_app_type] => new [patent_app_number] => 10/028077 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15136 [patent_no_of_claims] => 150 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091890.pdf [firstpage_image] =>[orig_patent_app_number] => 10028077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028077
Synchronous memory device having automatic precharge Dec 20, 2001 Issued
Array ( [id] => 1214318 [patent_doc_number] => 06715020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Synchronous integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 10/037171 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15250 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715020.pdf [firstpage_image] =>[orig_patent_app_number] => 10037171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037171
Synchronous integrated circuit device Dec 20, 2001 Issued
Array ( [id] => 998992 [patent_doc_number] => 06915370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Domain partitioning in a multi-node system' [patent_app_type] => utility [patent_app_number] => 10/029554 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2482 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915370.pdf [firstpage_image] =>[orig_patent_app_number] => 10029554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029554
Domain partitioning in a multi-node system Dec 19, 2001 Issued
Array ( [id] => 971323 [patent_doc_number] => 06941404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Data transfer device, transaction system and method for exchanging control and I/O data with a data processing system' [patent_app_type] => utility [patent_app_number] => 10/025375 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6995 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/941/06941404.pdf [firstpage_image] =>[orig_patent_app_number] => 10025375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025375
Data transfer device, transaction system and method for exchanging control and I/O data with a data processing system Dec 17, 2001 Issued
Array ( [id] => 6698145 [patent_doc_number] => 20030110339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Chip to chip interface for interconnecting chips' [patent_app_type] => new [patent_app_number] => 10/016800 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9460 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110339.pdf [firstpage_image] =>[orig_patent_app_number] => 10016800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016800
Chip to chip interface for interconnecting chips Dec 9, 2001 Issued
Array ( [id] => 1058947 [patent_doc_number] => 06857040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Bi-directional bus bridge in which multiple devices can assert bus concurrently' [patent_app_type] => utility [patent_app_number] => 10/006878 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857040.pdf [firstpage_image] =>[orig_patent_app_number] => 10006878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/006878
Bi-directional bus bridge in which multiple devices can assert bus concurrently Dec 4, 2001 Issued
Array ( [id] => 1068292 [patent_doc_number] => 06848015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Arbitration technique based on processor task priority' [patent_app_type] => utility [patent_app_number] => 09/998514 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3161 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848015.pdf [firstpage_image] =>[orig_patent_app_number] => 09998514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998514
Arbitration technique based on processor task priority Nov 29, 2001 Issued
Array ( [id] => 1540509 [patent_doc_number] => 06490641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Addressable shadow port circuit' [patent_app_type] => B2 [patent_app_number] => 09/997327 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 49 [patent_no_of_words] => 43093 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490641.pdf [firstpage_image] =>[orig_patent_app_number] => 09997327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997327
Addressable shadow port circuit Nov 28, 2001 Issued
Array ( [id] => 6066279 [patent_doc_number] => 20020032825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Bus controlling system' [patent_app_type] => new [patent_app_number] => 09/991704 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4811 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032825.pdf [firstpage_image] =>[orig_patent_app_number] => 09991704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991704
Bus controlling system Nov 25, 2001 Issued
Array ( [id] => 1043137 [patent_doc_number] => 06871247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Mechanism for supporting self-modifying code in a harvard architecture digital signal processor and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 10/007555 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/871/06871247.pdf [firstpage_image] =>[orig_patent_app_number] => 10007555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007555
Mechanism for supporting self-modifying code in a harvard architecture digital signal processor and method of operation thereof Nov 7, 2001 Issued
Array ( [id] => 950042 [patent_doc_number] => 06963948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Microcomputer bridge architecture with an embedded microcontroller' [patent_app_type] => utility [patent_app_number] => 10/033142 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7680 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963948.pdf [firstpage_image] =>[orig_patent_app_number] => 10033142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033142
Microcomputer bridge architecture with an embedded microcontroller Oct 31, 2001 Issued
Array ( [id] => 6631891 [patent_doc_number] => 20020065972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Bus system for use with information processing apparatus' [patent_app_type] => new [patent_app_number] => 09/983373 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20020065972.pdf [firstpage_image] =>[orig_patent_app_number] => 09983373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983373
Bus system for use with information processing apparatus Oct 23, 2001 Issued
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