
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6348789
[patent_doc_number] => 20020035659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'Switching system'
[patent_app_type] => new
[patent_app_number] => 09/866749
[patent_app_country] => US
[patent_app_date] => 2001-05-30
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Array
(
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[patent_doc_number] => 07076595
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[patent_kind] => B1
[patent_issue_date] => 2006-07-11
[patent_title] => 'Programmable logic device including programmable interface core and central processing unit'
[patent_app_type] => utility
[patent_app_number] => 09/861112
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[patent_app_date] => 2001-05-18
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Array
(
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[patent_doc_number] => 20020012401
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[patent_issue_date] => 2002-01-31
[patent_title] => 'Transducer network bus'
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[patent_app_number] => 09/859798
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[patent_drawing_sheets_cnt] => 19
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2002-11-19
[patent_title] => 'Method and system for managing communications among computer devices'
[patent_app_type] => B2
[patent_app_number] => 09/854236
[patent_app_country] => US
[patent_app_date] => 2001-05-11
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[patent_drawing_sheets_cnt] => 3
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Array
(
[id] => 6051376
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[patent_issue_date] => 2002-11-14
[patent_title] => ' System and method of switching a hot-pluggable peripheral device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/852981 | System and method of switching a hot-pluggable peripheral device | May 9, 2001 | Abandoned |
Array
(
[id] => 1186642
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[patent_issue_date] => 2004-05-18
[patent_title] => 'Real-time communications for speeding up packet transmission'
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[patent_app_number] => 09/842279
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/842279 | Real-time communications for speeding up packet transmission | Apr 23, 2001 | Issued |
Array
(
[id] => 1169714
[patent_doc_number] => 06766398
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[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Method for processing PCI interrupt signals in a logically partitioned guest operating system'
[patent_app_type] => B2
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[patent_app_date] => 2001-04-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/836687 | Method for processing PCI interrupt signals in a logically partitioned guest operating system | Apr 16, 2001 | Issued |
Array
(
[id] => 6894522
[patent_doc_number] => 20010016888
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[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment'
[patent_app_type] => new
[patent_app_number] => 09/835578
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/835578 | Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment | Apr 16, 2001 | Abandoned |
Array
(
[id] => 6901883
[patent_doc_number] => 20010023466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-20
[patent_title] => 'Memory device having a programmable register'
[patent_app_type] => new
[patent_app_number] => 09/835263
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[firstpage_image] =>[orig_patent_app_number] => 09835263
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/835263 | Memory device having a programmable register | Apr 12, 2001 | Issued |
Array
(
[id] => 6892561
[patent_doc_number] => 20010018723
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[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Storage medium having electronic circuit and computer system having the storage medium'
[patent_app_type] => new
[patent_app_number] => 09/814289
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[patent_app_date] => 2001-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/814289 | Storage medium having electronic circuit and computer system having the storage medium | Mar 20, 2001 | Issued |
Array
(
[id] => 7321093
[patent_doc_number] => 20040225777
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[patent_issue_date] => 2004-11-11
[patent_title] => 'Memory repeater'
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Array
(
[id] => 6450858
[patent_doc_number] => 20020129184
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[patent_title] => 'Effective bus utilization using bus arbiter'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802417 | Effective bus utilization using multiple bus interface circuits and arbitration logic circuit | Mar 7, 2001 | Issued |
| 90/005932 | COMMUNICATION INTERFACE CIRCUIT HAVING NETWORK CONNECTION DETECTION CAPABILITY | Feb 19, 2001 | Issued |
Array
(
[id] => 6565266
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Array
(
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[patent_title] => 'REDUCED COMPLEXITY COMPUTER SYSTEM ARCHITECTURE'
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Array
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Array
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Array
(
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Array
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Array
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