Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1466732 [patent_doc_number] => 06351819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Heterogeneous system enclosure services connection' [patent_app_type] => B1 [patent_app_number] => 09/267778 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5284 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351819.pdf [firstpage_image] =>[orig_patent_app_number] => 09267778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267778
Heterogeneous system enclosure services connection Mar 14, 1999 Issued
Array ( [id] => 4381038 [patent_doc_number] => 06256695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Disk drive method of determining SCSI bus state information after a SCSI bus reset condition' [patent_app_type] => 1 [patent_app_number] => 9/268620 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3992 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256695.pdf [firstpage_image] =>[orig_patent_app_number] => 268620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268620
Disk drive method of determining SCSI bus state information after a SCSI bus reset condition Mar 14, 1999 Issued
Array ( [id] => 1466636 [patent_doc_number] => 06351779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Extension library to standard visa library for support of complex I/O functions' [patent_app_type] => B1 [patent_app_number] => 09/266997 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4330 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351779.pdf [firstpage_image] =>[orig_patent_app_number] => 09266997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266997
Extension library to standard visa library for support of complex I/O functions Mar 11, 1999 Issued
Array ( [id] => 4391395 [patent_doc_number] => 06289405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Addition of slot, backplane, chassis and device parametric properties to vital product data (VPD) in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/265394 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 4 [patent_no_of_words] => 7513 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289405.pdf [firstpage_image] =>[orig_patent_app_number] => 265394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265394
Addition of slot, backplane, chassis and device parametric properties to vital product data (VPD) in a computer system Mar 9, 1999 Issued
Array ( [id] => 4162096 [patent_doc_number] => 06032215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Synchronous memory device utilizing two external clocks' [patent_app_type] => 1 [patent_app_number] => 9/263224 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15173 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032215.pdf [firstpage_image] =>[orig_patent_app_number] => 263224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263224
Synchronous memory device utilizing two external clocks Mar 4, 1999 Issued
Array ( [id] => 7645918 [patent_doc_number] => 06477605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Apparatus and method for controlling device connection' [patent_app_type] => B1 [patent_app_number] => 09/262007 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 9666 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477605.pdf [firstpage_image] =>[orig_patent_app_number] => 09262007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262007
Apparatus and method for controlling device connection Mar 3, 1999 Issued
Array ( [id] => 1604465 [patent_doc_number] => 06434651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for suppressing interrupts in a high-speed network environment' [patent_app_type] => B1 [patent_app_number] => 09/260367 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13719 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434651.pdf [firstpage_image] =>[orig_patent_app_number] => 09260367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260367
Method and apparatus for suppressing interrupts in a high-speed network environment Feb 28, 1999 Issued
Array ( [id] => 1490071 [patent_doc_number] => 06366975 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Large-scale integrated circuit (LSI) circuit for controlling electronic device including LSI, and method of controlling the circuit' [patent_app_type] => B1 [patent_app_number] => 09/258579 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6109 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366975.pdf [firstpage_image] =>[orig_patent_app_number] => 09258579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258579
Large-scale integrated circuit (LSI) circuit for controlling electronic device including LSI, and method of controlling the circuit Feb 25, 1999 Issued
Array ( [id] => 1549531 [patent_doc_number] => 06374322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Bus controlling system' [patent_app_type] => B1 [patent_app_number] => 09/256177 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4741 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374322.pdf [firstpage_image] =>[orig_patent_app_number] => 09256177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256177
Bus controlling system Feb 23, 1999 Issued
Array ( [id] => 4400145 [patent_doc_number] => 06304938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Detecting a state change in a lock structure to validate a potential deadlock' [patent_app_type] => 1 [patent_app_number] => 9/256330 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5007 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304938.pdf [firstpage_image] =>[orig_patent_app_number] => 256330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256330
Detecting a state change in a lock structure to validate a potential deadlock Feb 22, 1999 Issued
Array ( [id] => 1567343 [patent_doc_number] => 06363443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Addressable shadow port and protocol for serial bus networks' [patent_app_type] => B1 [patent_app_number] => 09/253505 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 49 [patent_no_of_words] => 43156 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363443.pdf [firstpage_image] =>[orig_patent_app_number] => 09253505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253505
Addressable shadow port and protocol for serial bus networks Feb 18, 1999 Issued
Array ( [id] => 4194605 [patent_doc_number] => 06085267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method of and apparatus for recording information on record medium, and apparatus for reproducing the same' [patent_app_type] => 1 [patent_app_number] => 9/244778 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8969 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085267.pdf [firstpage_image] =>[orig_patent_app_number] => 244778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244778
Method of and apparatus for recording information on record medium, and apparatus for reproducing the same Feb 4, 1999 Issued
Array ( [id] => 4211134 [patent_doc_number] => 06044426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Memory system having memory devices each including a programmable internal register' [patent_app_type] => 1 [patent_app_number] => 9/239522 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15139 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044426.pdf [firstpage_image] =>[orig_patent_app_number] => 239522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239522
Memory system having memory devices each including a programmable internal register Jan 28, 1999 Issued
Array ( [id] => 4349430 [patent_doc_number] => 06321288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Serial IRQ slave controller with auto-synchronization' [patent_app_type] => 1 [patent_app_number] => 9/238199 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321288.pdf [firstpage_image] =>[orig_patent_app_number] => 238199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238199
Serial IRQ slave controller with auto-synchronization Jan 25, 1999 Issued
Array ( [id] => 1366320 [patent_doc_number] => 06584534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Combined isochronous and asynchronous communication apparatus, method and interface' [patent_app_type] => B1 [patent_app_number] => 09/236222 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6276 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584534.pdf [firstpage_image] =>[orig_patent_app_number] => 09236222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236222
Combined isochronous and asynchronous communication apparatus, method and interface Jan 24, 1999 Issued
Array ( [id] => 4423315 [patent_doc_number] => 06311247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'System for bridging a system bus with multiple PCI buses' [patent_app_type] => 1 [patent_app_number] => 9/232193 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311247.pdf [firstpage_image] =>[orig_patent_app_number] => 232193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232193
System for bridging a system bus with multiple PCI buses Jan 14, 1999 Issued
Array ( [id] => 4291993 [patent_doc_number] => 06247083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for bi-directionally transferring data between an IEEE 1394 bus and a device to be controlled by a control signal transmitted via the bus' [patent_app_type] => 1 [patent_app_number] => 9/232108 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2690 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247083.pdf [firstpage_image] =>[orig_patent_app_number] => 232108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232108
Method and apparatus for bi-directionally transferring data between an IEEE 1394 bus and a device to be controlled by a control signal transmitted via the bus Jan 14, 1999 Issued
Array ( [id] => 655217 [patent_doc_number] => RE039284 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2006-09-12 [patent_title] => 'Method and apparatus for reducing power consumption in a system using power management software capable of placing multiple configurable system devices in a reduced power consumption state' [patent_app_type] => reissue [patent_app_number] => 09/224620 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6281 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/039/RE039284.pdf [firstpage_image] =>[orig_patent_app_number] => 09224620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224620
Method and apparatus for reducing power consumption in a system using power management software capable of placing multiple configurable system devices in a reduced power consumption state Dec 30, 1998 Issued
Array ( [id] => 1495246 [patent_doc_number] => 06418497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and system for interrupt handling using system pipelined packet transfers' [patent_app_type] => B1 [patent_app_number] => 09/224119 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4217 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418497.pdf [firstpage_image] =>[orig_patent_app_number] => 09224119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224119
Method and system for interrupt handling using system pipelined packet transfers Dec 20, 1998 Issued
Array ( [id] => 4423625 [patent_doc_number] => 06240481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Data bus control for image forming apparatus' [patent_app_type] => 1 [patent_app_number] => 9/216443 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11980 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240481.pdf [firstpage_image] =>[orig_patent_app_number] => 216443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216443
Data bus control for image forming apparatus Dec 17, 1998 Issued
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