Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4292096 [patent_doc_number] => 06247089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Efficient data loading scheme to minimize PCI bus arbitrations delays and wait states' [patent_app_type] => 1 [patent_app_number] => 9/154076 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10239 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247089.pdf [firstpage_image] =>[orig_patent_app_number] => 154076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154076
Efficient data loading scheme to minimize PCI bus arbitrations delays and wait states Sep 15, 1998 Issued
Array ( [id] => 4116481 [patent_doc_number] => 06067627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Core section having asynchronous partial reset' [patent_app_type] => 1 [patent_app_number] => 9/144319 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8041 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067627.pdf [firstpage_image] =>[orig_patent_app_number] => 144319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144319
Core section having asynchronous partial reset Aug 30, 1998 Issued
Array ( [id] => 3945062 [patent_doc_number] => 05935231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Bus system for use with information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/143985 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7040 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935231.pdf [firstpage_image] =>[orig_patent_app_number] => 143985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143985
Bus system for use with information processing apparatus Aug 30, 1998 Issued
Array ( [id] => 4155618 [patent_doc_number] => 06122693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'PCI bus utilization diagnostic monitor' [patent_app_type] => 1 [patent_app_number] => 9/140672 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4128 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122693.pdf [firstpage_image] =>[orig_patent_app_number] => 140672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140672
PCI bus utilization diagnostic monitor Aug 25, 1998 Issued
Array ( [id] => 4260066 [patent_doc_number] => 06167479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'System and method for testing interrupt processing logic within an instruction processor' [patent_app_type] => 1 [patent_app_number] => 9/128297 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14661 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167479.pdf [firstpage_image] =>[orig_patent_app_number] => 128297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128297
System and method for testing interrupt processing logic within an instruction processor Aug 2, 1998 Issued
Array ( [id] => 4310735 [patent_doc_number] => 06212641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and apparatus for improving power characteristics in a system having a reduced power mode' [patent_app_type] => 1 [patent_app_number] => 9/121648 [patent_app_country] => US [patent_app_date] => 1998-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1518 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212641.pdf [firstpage_image] =>[orig_patent_app_number] => 121648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/121648
Method and apparatus for improving power characteristics in a system having a reduced power mode Jul 22, 1998 Issued
Array ( [id] => 4427282 [patent_doc_number] => 06226705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Integrated network switching hub and bus structure' [patent_app_type] => 1 [patent_app_number] => 9/115409 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4119 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226705.pdf [firstpage_image] =>[orig_patent_app_number] => 115409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115409
Integrated network switching hub and bus structure Jul 13, 1998 Issued
Array ( [id] => 4192261 [patent_doc_number] => 06141714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method and apparatus for executing self-snooped unresolvable system bus operations' [patent_app_type] => 1 [patent_app_number] => 9/114209 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5741 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141714.pdf [firstpage_image] =>[orig_patent_app_number] => 114209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114209
Method and apparatus for executing self-snooped unresolvable system bus operations Jul 12, 1998 Issued
Array ( [id] => 4370897 [patent_doc_number] => 06216192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Dynamic resource allocation across bus bridges' [patent_app_type] => 1 [patent_app_number] => 9/107940 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2131 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216192.pdf [firstpage_image] =>[orig_patent_app_number] => 107940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107940
Dynamic resource allocation across bus bridges Jun 29, 1998 Issued
Array ( [id] => 4223654 [patent_doc_number] => 06078979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Selective isolation of a storage subsystem bus utilzing a subsystem controller' [patent_app_type] => 1 [patent_app_number] => 9/100048 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5294 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078979.pdf [firstpage_image] =>[orig_patent_app_number] => 100048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100048
Selective isolation of a storage subsystem bus utilzing a subsystem controller Jun 18, 1998 Issued
Array ( [id] => 4162034 [patent_doc_number] => 06032211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of mode control in a bus optimized for personal computer data traffic' [patent_app_type] => 1 [patent_app_number] => 9/099227 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9237 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032211.pdf [firstpage_image] =>[orig_patent_app_number] => 099227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099227
Method of mode control in a bus optimized for personal computer data traffic Jun 16, 1998 Issued
Array ( [id] => 4259541 [patent_doc_number] => 06092138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Electronic apparatus having a high-speed communication bus system such as an I.sup.2 C bus system' [patent_app_type] => 1 [patent_app_number] => 9/098765 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9887 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092138.pdf [firstpage_image] =>[orig_patent_app_number] => 098765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098765
Electronic apparatus having a high-speed communication bus system such as an I.sup.2 C bus system Jun 16, 1998 Issued
Array ( [id] => 4203866 [patent_doc_number] => 06151651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/098360 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 9689 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151651.pdf [firstpage_image] =>[orig_patent_app_number] => 098360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098360
Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system Jun 16, 1998 Issued
Array ( [id] => 3923247 [patent_doc_number] => 05928343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Memory module having memory devices containing internal device ID registers and method of initializing same' [patent_app_type] => 1 [patent_app_number] => 9/098387 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 15130 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928343.pdf [firstpage_image] =>[orig_patent_app_number] => 098387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098387
Memory module having memory devices containing internal device ID registers and method of initializing same Jun 15, 1998 Issued
Array ( [id] => 4147237 [patent_doc_number] => 06128686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Hiding peripheral memory transactions on a local bus within a peripheral controller from a host system bus' [patent_app_type] => 1 [patent_app_number] => 9/097408 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4294 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128686.pdf [firstpage_image] =>[orig_patent_app_number] => 097408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097408
Hiding peripheral memory transactions on a local bus within a peripheral controller from a host system bus Jun 14, 1998 Issued
Array ( [id] => 4268909 [patent_doc_number] => 06138198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses' [patent_app_type] => 1 [patent_app_number] => 9/097467 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14963 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138198.pdf [firstpage_image] =>[orig_patent_app_number] => 097467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097467
Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses Jun 14, 1998 Issued
Array ( [id] => 4192322 [patent_doc_number] => 06141718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses' [patent_app_type] => 1 [patent_app_number] => 9/097487 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14620 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141718.pdf [firstpage_image] =>[orig_patent_app_number] => 097487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097487
Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data direct memory accesses Jun 14, 1998 Issued
Array ( [id] => 4118079 [patent_doc_number] => 06098140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Modular bus bridge system compatible with multiple bus pin configurations' [patent_app_type] => 1 [patent_app_number] => 9/096096 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098140.pdf [firstpage_image] =>[orig_patent_app_number] => 096096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096096
Modular bus bridge system compatible with multiple bus pin configurations Jun 10, 1998 Issued
Array ( [id] => 984588 [patent_doc_number] => 06928503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and apparatus for robust addressing on a dynamically configurable bus' [patent_app_type] => utility [patent_app_number] => 09/095032 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5806 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928503.pdf [firstpage_image] =>[orig_patent_app_number] => 09095032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095032
Method and apparatus for robust addressing on a dynamically configurable bus Jun 9, 1998 Issued
Array ( [id] => 4122483 [patent_doc_number] => 06052793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Wakeup event restoration after power loss' [patent_app_type] => 1 [patent_app_number] => 9/095354 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2885 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052793.pdf [firstpage_image] =>[orig_patent_app_number] => 095354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095354
Wakeup event restoration after power loss Jun 9, 1998 Issued
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