
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4325183
[patent_doc_number] => 06253272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Execution suspension and resumption in multi-tasking host adapters'
[patent_app_type] => 1
[patent_app_number] => 9/088810
[patent_app_country] => US
[patent_app_date] => 1998-06-02
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[pdf_file] => patents/06/253/06253272.pdf
[firstpage_image] =>[orig_patent_app_number] => 088810
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088810 | Execution suspension and resumption in multi-tasking host adapters | Jun 1, 1998 | Issued |
Array
(
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[patent_doc_number] => 06112272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters'
[patent_app_type] => 1
[patent_app_number] => 9/096300
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[patent_app_date] => 1998-06-02
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[firstpage_image] =>[orig_patent_app_number] => 096300
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/096300 | Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters | Jun 1, 1998 | Issued |
Array
(
[id] => 4151501
[patent_doc_number] => 06035359
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method and system for controlling message display upon insertion and removal of a PC card into and from a computer system'
[patent_app_type] => 1
[patent_app_number] => 9/086569
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[patent_app_date] => 1998-05-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086569 | Method and system for controlling message display upon insertion and removal of a PC card into and from a computer system | May 28, 1998 | Issued |
Array
(
[id] => 4148125
[patent_doc_number] => 06128745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Power management inactivity monitoring using software threads'
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[patent_app_number] => 9/084915
[patent_app_country] => US
[patent_app_date] => 1998-05-28
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Array
(
[id] => 3932704
[patent_doc_number] => 06003106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'DMA cache control logic'
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[patent_app_date] => 1998-05-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/085195 | DMA cache control logic | May 26, 1998 | Issued |
Array
(
[id] => 4156455
[patent_doc_number] => 06122744
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[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Selecting a routine based on processing power'
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[firstpage_image] =>[orig_patent_app_number] => 082140
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/082140 | Selecting a routine based on processing power | May 19, 1998 | Issued |
Array
(
[id] => 4237135
[patent_doc_number] => 06112271
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Multiconfiguration backplane'
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[pdf_file] => patents/06/112/06112271.pdf
[firstpage_image] =>[orig_patent_app_number] => 079040
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/079040 | Multiconfiguration backplane | May 13, 1998 | Issued |
Array
(
[id] => 4257423
[patent_doc_number] => 06081901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'System and method for dynamically controlling processing speed of a computer in response to user commands'
[patent_app_type] => 1
[patent_app_number] => 9/073808
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[patent_app_date] => 1998-05-07
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[pdf_file] => patents/06/081/06081901.pdf
[firstpage_image] =>[orig_patent_app_number] => 073808
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073808 | System and method for dynamically controlling processing speed of a computer in response to user commands | May 6, 1998 | Issued |
Array
(
[id] => 4268698
[patent_doc_number] => 06138183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Transparent direct memory access'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/074656 | Transparent direct memory access | May 5, 1998 | Issued |
Array
(
[id] => 4198920
[patent_doc_number] => 06038632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Interrupt control on SMM'
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[patent_app_number] => 9/073265
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Array
(
[id] => 4176941
[patent_doc_number] => 06105091
[patent_country] => US
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[patent_issue_date] => 2000-08-15
[patent_title] => 'Connector with integrated bus and power isolation switches'
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[firstpage_image] =>[orig_patent_app_number] => 071608
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071608 | Connector with integrated bus and power isolation switches | Apr 30, 1998 | Issued |
Array
(
[id] => 4269842
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[patent_issue_date] => 2001-04-24
[patent_title] => 'SCSI bus based high speed data server'
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Array
(
[id] => 4225697
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[patent_title] => 'Advanced programmable interrupt controller'
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Array
(
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[patent_title] => 'Remote multi-level control bus'
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[firstpage_image] =>[orig_patent_app_number] => 065430
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/065430 | Remote multi-level control bus | Apr 23, 1998 | Issued |
Array
(
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[patent_title] => 'Computer system having a screen saver with a power shutdown function and a control method thereof'
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Array
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Array
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[patent_issue_date] => 2000-07-04
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Array
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Array
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Array
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