Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4325183 [patent_doc_number] => 06253272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Execution suspension and resumption in multi-tasking host adapters' [patent_app_type] => 1 [patent_app_number] => 9/088810 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5814 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253272.pdf [firstpage_image] =>[orig_patent_app_number] => 088810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088810
Execution suspension and resumption in multi-tasking host adapters Jun 1, 1998 Issued
Array ( [id] => 4237150 [patent_doc_number] => 06112272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters' [patent_app_type] => 1 [patent_app_number] => 9/096300 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112272.pdf [firstpage_image] =>[orig_patent_app_number] => 096300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096300
Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters Jun 1, 1998 Issued
Array ( [id] => 4151501 [patent_doc_number] => 06035359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and system for controlling message display upon insertion and removal of a PC card into and from a computer system' [patent_app_type] => 1 [patent_app_number] => 9/086569 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1745 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035359.pdf [firstpage_image] =>[orig_patent_app_number] => 086569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086569
Method and system for controlling message display upon insertion and removal of a PC card into and from a computer system May 28, 1998 Issued
Array ( [id] => 4148125 [patent_doc_number] => 06128745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Power management inactivity monitoring using software threads' [patent_app_type] => 1 [patent_app_number] => 9/084915 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5838 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128745.pdf [firstpage_image] =>[orig_patent_app_number] => 084915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084915
Power management inactivity monitoring using software threads May 27, 1998 Issued
Array ( [id] => 3932704 [patent_doc_number] => 06003106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'DMA cache control logic' [patent_app_type] => 1 [patent_app_number] => 9/085195 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9845 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003106.pdf [firstpage_image] =>[orig_patent_app_number] => 085195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085195
DMA cache control logic May 26, 1998 Issued
Array ( [id] => 4156455 [patent_doc_number] => 06122744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Selecting a routine based on processing power' [patent_app_type] => 1 [patent_app_number] => 9/082140 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2900 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122744.pdf [firstpage_image] =>[orig_patent_app_number] => 082140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082140
Selecting a routine based on processing power May 19, 1998 Issued
Array ( [id] => 4237135 [patent_doc_number] => 06112271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Multiconfiguration backplane' [patent_app_type] => 1 [patent_app_number] => 9/079040 [patent_app_country] => US [patent_app_date] => 1998-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4727 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112271.pdf [firstpage_image] =>[orig_patent_app_number] => 079040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079040
Multiconfiguration backplane May 13, 1998 Issued
Array ( [id] => 4257423 [patent_doc_number] => 06081901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'System and method for dynamically controlling processing speed of a computer in response to user commands' [patent_app_type] => 1 [patent_app_number] => 9/073808 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6126 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081901.pdf [firstpage_image] =>[orig_patent_app_number] => 073808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073808
System and method for dynamically controlling processing speed of a computer in response to user commands May 6, 1998 Issued
Array ( [id] => 4268698 [patent_doc_number] => 06138183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Transparent direct memory access' [patent_app_type] => 1 [patent_app_number] => 9/074656 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6036 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138183.pdf [firstpage_image] =>[orig_patent_app_number] => 074656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074656
Transparent direct memory access May 5, 1998 Issued
Array ( [id] => 4198920 [patent_doc_number] => 06038632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Interrupt control on SMM' [patent_app_type] => 1 [patent_app_number] => 9/073265 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 11968 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038632.pdf [firstpage_image] =>[orig_patent_app_number] => 073265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073265
Interrupt control on SMM May 5, 1998 Issued
Array ( [id] => 4176941 [patent_doc_number] => 06105091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Connector with integrated bus and power isolation switches' [patent_app_type] => 1 [patent_app_number] => 9/071608 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1248 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105091.pdf [firstpage_image] =>[orig_patent_app_number] => 071608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071608
Connector with integrated bus and power isolation switches Apr 30, 1998 Issued
Array ( [id] => 4269842 [patent_doc_number] => 06223235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'SCSI bus based high speed data server' [patent_app_type] => 1 [patent_app_number] => 9/070202 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 13727 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223235.pdf [firstpage_image] =>[orig_patent_app_number] => 070202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070202
SCSI bus based high speed data server Apr 29, 1998 Issued
Array ( [id] => 4225697 [patent_doc_number] => 06029223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Advanced programmable interrupt controller' [patent_app_type] => 1 [patent_app_number] => 9/067338 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4292 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029223.pdf [firstpage_image] =>[orig_patent_app_number] => 067338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067338
Advanced programmable interrupt controller Apr 26, 1998 Issued
Array ( [id] => 4257340 [patent_doc_number] => 06145041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Remote multi-level control bus' [patent_app_type] => 1 [patent_app_number] => 9/065430 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1389 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145041.pdf [firstpage_image] =>[orig_patent_app_number] => 065430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/065430
Remote multi-level control bus Apr 23, 1998 Issued
Array ( [id] => 4252842 [patent_doc_number] => 06076169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Computer system having a screen saver with a power shutdown function and a control method thereof' [patent_app_type] => 1 [patent_app_number] => 9/062721 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2522 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076169.pdf [firstpage_image] =>[orig_patent_app_number] => 062721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062721
Computer system having a screen saver with a power shutdown function and a control method thereof Apr 19, 1998 Issued
Array ( [id] => 4177576 [patent_doc_number] => 06108744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Software interrupt mechanism' [patent_app_type] => 1 [patent_app_number] => 9/062784 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6062 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108744.pdf [firstpage_image] =>[orig_patent_app_number] => 062784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062784
Software interrupt mechanism Apr 15, 1998 Issued
Array ( [id] => 4195467 [patent_doc_number] => 06085327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized' [patent_app_type] => 1 [patent_app_number] => 9/058124 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2429 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 668 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085327.pdf [firstpage_image] =>[orig_patent_app_number] => 058124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058124
Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized Apr 9, 1998 Issued
Array ( [id] => 4203487 [patent_doc_number] => 06161158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Bus arbitration apparatus and method wherein each module has two in-module arbiters' [patent_app_type] => 1 [patent_app_number] => 9/056850 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3069 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161158.pdf [firstpage_image] =>[orig_patent_app_number] => 056850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056850
Bus arbitration apparatus and method wherein each module has two in-module arbiters Apr 7, 1998 Issued
Array ( [id] => 4109743 [patent_doc_number] => 06134617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and apparatus for managing access to a loop in a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/054850 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 12156 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134617.pdf [firstpage_image] =>[orig_patent_app_number] => 054850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054850
Method and apparatus for managing access to a loop in a data processing system Apr 2, 1998 Issued
Array ( [id] => 4156509 [patent_doc_number] => 06122748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Control of computer system wake/sleep transitions' [patent_app_type] => 1 [patent_app_number] => 9/052439 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3111 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122748.pdf [firstpage_image] =>[orig_patent_app_number] => 052439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052439
Control of computer system wake/sleep transitions Mar 30, 1998 Issued
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