Search

Glenn Allen Auve

Examiner (ID: 4388, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2781, 2111, 2181, 2185, 2305, 2175, 2308, 2186
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 944301 [patent_doc_number] => 06967355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Group III-nitride on Si using epitaxial BP buffer layer' [patent_app_type] => utility [patent_app_number] => 10/691055 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3269 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967355.pdf [firstpage_image] =>[orig_patent_app_number] => 10691055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691055
Group III-nitride on Si using epitaxial BP buffer layer Oct 21, 2003 Issued
Array ( [id] => 761927 [patent_doc_number] => 07012279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Photonic crystal light emitting device' [patent_app_type] => utility [patent_app_number] => 10/691026 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6396 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012279.pdf [firstpage_image] =>[orig_patent_app_number] => 10691026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691026
Photonic crystal light emitting device Oct 20, 2003 Issued
Array ( [id] => 7328791 [patent_doc_number] => 20040129940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Semiconductor wafer and a methd for manufacturing a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/687705 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8798 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20040129940.pdf [firstpage_image] =>[orig_patent_app_number] => 10687705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687705
Semiconductor wafer and a method for manufacturing a semiconductor wafer Oct 19, 2003 Issued
Array ( [id] => 7371780 [patent_doc_number] => 20040080002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Boron incorporated diffusion barrier material' [patent_app_type] => new [patent_app_number] => 10/687086 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3954 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080002.pdf [firstpage_image] =>[orig_patent_app_number] => 10687086 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687086
Boron incorporated diffusion barrier material Oct 15, 2003 Issued
Array ( [id] => 7154365 [patent_doc_number] => 20050082592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Compact capacitor structure having high unit capacitance' [patent_app_type] => utility [patent_app_number] => 10/686866 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3807 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082592.pdf [firstpage_image] =>[orig_patent_app_number] => 10686866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686866
Compact capacitor structure having high unit capacitance Oct 15, 2003 Abandoned
Array ( [id] => 442769 [patent_doc_number] => 07256074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods' [patent_app_type] => utility [patent_app_number] => 10/687096 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4344 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256074.pdf [firstpage_image] =>[orig_patent_app_number] => 10687096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687096
Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods Oct 14, 2003 Issued
Array ( [id] => 5735944 [patent_doc_number] => 20060006334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Memory element and memory device' [patent_app_type] => utility [patent_app_number] => 10/530006 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11418 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006334.pdf [firstpage_image] =>[orig_patent_app_number] => 10530006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/530006
Memory element and memory device Oct 1, 2003 Issued
Array ( [id] => 7204914 [patent_doc_number] => 20040070033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Semiconductor device with resistor pattern and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/675336 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070033.pdf [firstpage_image] =>[orig_patent_app_number] => 10675336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675336
Semiconductor device with resistor pattern and method of fabricating the same Sep 28, 2003 Issued
Array ( [id] => 7465101 [patent_doc_number] => 20040095803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Fluxon injection into annular josephson junctions' [patent_app_type] => new [patent_app_number] => 10/671651 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5757 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095803.pdf [firstpage_image] =>[orig_patent_app_number] => 10671651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/671651
Fluxon injection into annular josephson junctions Sep 25, 2003 Abandoned
Array ( [id] => 7445486 [patent_doc_number] => 20040051124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Solid state image sensor having planarized structure under light shielding metal layer' [patent_app_type] => new [patent_app_number] => 10/657236 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20040051124.pdf [firstpage_image] =>[orig_patent_app_number] => 10657236 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657236
Solid state image sensor having planarized structure under light shielding metal layer Sep 8, 2003 Issued
Array ( [id] => 397886 [patent_doc_number] => 07294855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/653556 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 49 [patent_no_of_words] => 11829 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294855.pdf [firstpage_image] =>[orig_patent_app_number] => 10653556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653556
Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof Sep 1, 2003 Issued
Array ( [id] => 1046752 [patent_doc_number] => 06864146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Metal oxide integrated circuit on silicon germanium substrate' [patent_app_type] => utility [patent_app_number] => 10/651796 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864146.pdf [firstpage_image] =>[orig_patent_app_number] => 10651796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651796
Metal oxide integrated circuit on silicon germanium substrate Aug 27, 2003 Issued
Array ( [id] => 790823 [patent_doc_number] => 06984846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Gradiometer-based flux qubit for quantum computing and method therefor' [patent_app_type] => utility [patent_app_number] => 10/648346 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5273 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/984/06984846.pdf [firstpage_image] =>[orig_patent_app_number] => 10648346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648346
Gradiometer-based flux qubit for quantum computing and method therefor Aug 26, 2003 Issued
Array ( [id] => 759074 [patent_doc_number] => 07015497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-21 [patent_title] => 'Self-aligned and self-limited quantum dot nanoswitches and methods for making same' [patent_app_type] => utility [patent_app_number] => 10/649046 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 20 [patent_no_of_words] => 6053 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015497.pdf [firstpage_image] =>[orig_patent_app_number] => 10649046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649046
Self-aligned and self-limited quantum dot nanoswitches and methods for making same Aug 26, 2003 Issued
Array ( [id] => 7234315 [patent_doc_number] => 20040256612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Electrically tunable quantum dots and methods for making and using for same' [patent_app_type] => new [patent_app_number] => 10/642095 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4585 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20040256612.pdf [firstpage_image] =>[orig_patent_app_number] => 10642095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642095
Electrically tunable quantum dots and methods for making and using same Aug 14, 2003 Issued
Array ( [id] => 7301161 [patent_doc_number] => 20040113138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Stochastic assembly of sublithographic nanoscale interfaces' [patent_app_type] => new [patent_app_number] => 10/627405 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11136 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113138.pdf [firstpage_image] =>[orig_patent_app_number] => 10627405 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627405
Stochastic assembly of sublithographic nanoscale interfaces Jul 23, 2003 Issued
Array ( [id] => 7295851 [patent_doc_number] => 20040124447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'III-V single crystal as well as method of producing the same, and semiconductor device utilizing the III-V single crystal' [patent_app_type] => new [patent_app_number] => 10/624612 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2898 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124447.pdf [firstpage_image] =>[orig_patent_app_number] => 10624612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624612
III-V single crystal as well as method of producing the same, and semiconductor device utilizing the III-V single crystal Jul 22, 2003 Issued
Array ( [id] => 383056 [patent_doc_number] => 07307008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole' [patent_app_type] => utility [patent_app_number] => 10/622915 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4297 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307008.pdf [firstpage_image] =>[orig_patent_app_number] => 10622915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622915
Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole Jul 17, 2003 Issued
Array ( [id] => 7120331 [patent_doc_number] => 20050012160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Etching metal silicides and germanides' [patent_app_type] => utility [patent_app_number] => 10/622955 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 942 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012160.pdf [firstpage_image] =>[orig_patent_app_number] => 10622955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622955
Etching metal silicides and germanides Jul 17, 2003 Issued
Array ( [id] => 485481 [patent_doc_number] => 07217608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-15 [patent_title] => 'CMOS with strained silicon channel NMOS and silicon germanium channel PMOS' [patent_app_type] => utility [patent_app_number] => 10/620605 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2928 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217608.pdf [firstpage_image] =>[orig_patent_app_number] => 10620605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620605
CMOS with strained silicon channel NMOS and silicon germanium channel PMOS Jul 16, 2003 Issued
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